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AD7817ARUZ

更新时间： 2024-01-20 12:29:13
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管输出元件传感器换能器
页数 文件大小 规格书
21页 2647K
描述
4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, MO-153-AB, TSSOP-16

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AD7817ARUZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknown风险等级：5.64
最大模拟输入电压：2.625 V最小模拟输入电压：
最长转换时间：9 µs转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm最大线性误差 (EL)：0.0977%
湿度敏感等级：1模拟输入通道数量：4
位数：10功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出位码：BINARY
输出格式：SERIAL封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
采样速率：0.1 MHz采样并保持/跟踪并保持：TRACK
座面最大高度：1.2 mm标称供电电压：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm
Base Number Matches：1

AD7817ARUZ 数据手册

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AD7817/AD7818  
Data Sheet  
TIMING CHARACTERISTICS  
VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Sample tested during initial  
release and after any redesign or process changes that may affect the parameters. All input signals are measured with tr = tf = 1 ns (10% to  
90% of 5 V) and timed from a voltage level of 1.6 V. See Figure 17, Figure 18, Figure 21, and Figure 22.  
Table 2.  
Parameter  
A Version/B Version  
Unit  
Test Conditions/Comments  
tPOWER-UP  
2
µs max  
µs max  
µs max  
ns min  
ns max  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns max  
ns max  
ns max  
ns max  
ns max  
ns min  
ns min  
Power-up time from rising edge of CONVST  
Conversion time Channel 1 to Channel 4  
Conversion time temperature sensor  
CONVST pulse width  
t1a  
t1b  
t2  
9
27  
20  
50  
0
t3  
CONVST falling edge to BUSY rising edge  
CS falling edge to RD/WR falling edge setup time  
RD/WR falling edge to SCLK falling edge setup  
DIN setup time before SCLK rising edge  
DIN hold time after SCLK rising edge  
t4  
t5  
0
t6  
t7  
t8  
t9  
10  
10  
40  
40  
0
SCLK low pulse width  
SCLK high pulse width  
t10  
t11  
CS falling edge to RD/WR rising edge setup time  
RD/WR rising edge to SCLK falling edge setup time  
DOUT access time after RD/WR rising edge  
DOUT access time after SCLK falling edge  
DOUT bus relinquish time after falling edge of RD/WR  
DOUT bus relinquish time after rising edge of CS  
BUSY falling edge to OTI falling edge  
RD/WR rising edge to OTI rising edge  
SCLK rising edge to CONVST falling edge (acquisition time of T/H)  
0
1
t12  
1
20  
20  
30  
30  
150  
40  
400  
t13  
1, 2  
t14a  
1, 2  
t14b  
t15  
t16  
t17  
1 These figures are measured with the load circuit of Figure 3. They are defined as the time required for DOUT to cross 0.8 V or 2.4 V for VDD = 5 V 10% and 0.4 V or 2 V for  
VDD = 3 V 10%, as shown in Table 1.  
2 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then  
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus  
relinquish times of the part and as such are independent of the external bus loading capacitances.  
200µA  
I
OL  
TO OUTPUT  
PIN  
1.6V  
C
L
50pF  
200µA  
I
OL  
Figure 3. Load Circuit for Access Time and Bus Relinquish Time  
Rev. D | Page 6 of 20  
 
 
 
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