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AD7817AR-REEL7 PDF预览

AD7817AR-REEL7

更新时间： 2024-01-04 21:43:17
品牌 Logo 应用领域
亚德诺 - ADI 传感器换能器温度传感器输出元件
页数 文件大小 规格书
20页 269K
描述
Single- and 4-Channel, 9 us, 10-Bit ADCs with On-Chip Temperature Sensor

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AD7817AR-REEL7 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：0.150 INCH, LEAD FREE, MS-012AC, SOIC-16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.74Is Samacsys：N
最大精度（摄氏度）：2 Cel主体宽度：3.9 mm
主体高度：1.55 mm主体长度或直径：9.9 mm
JESD-609代码：e0安装特点：SURFACE MOUNT
位数：10端子数量：16
最大工作电流：2 mA最高工作温度：85 °C
最低工作温度：-40 °C输出接口类型：3-WIRE INTERFACE
封装主体材料：PLASTIC/EPOXY封装等效代码：SOP16,.25
封装形状/形式：RECTANGULAR电源：3/5 V
传感器/换能器类型：TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL子类别：Other Sensors
最大供电电压：5.5 V最小供电电压：2.7 V
表面贴装：YES端子面层：Tin/Lead (Sn85Pb15)
端接类型：SOLDERBase Number Matches：1

AD7817AR-REEL7 数据手册

 浏览型号AD7817AR-REEL7的Datasheet PDF文件第2页浏览型号AD7817AR-REEL7的Datasheet PDF文件第3页浏览型号AD7817AR-REEL7的Datasheet PDF文件第4页浏览型号AD7817AR-REEL7的Datasheet PDF文件第6页浏览型号AD7817AR-REEL7的Datasheet PDF文件第7页浏览型号AD7817AR-REEL7的Datasheet PDF文件第8页 
AD7816/AD7817/AD7818  
(VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.5 V. All specifications TMIN to TMAX unless  
otherwise noted)  
TIMING CHARACTERISTICS1, 2  
Parameter  
A, B Versions  
Unit  
Test Conditions/Comments  
tPOWER-UP  
2
9
27  
20  
50  
0
µs max  
µs max  
µs max  
ns min  
ns max  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns max  
ns max  
ns max  
ns max  
ns max  
ns min  
ns min  
Power-Up Time from Rising Edge of CONVST  
Conversion Time Channels 1 to 4  
Conversion Time Temperature Sensor  
t1a  
t1b  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
CONVST Pulse Width  
CONVST Falling Edge to BUSY Rising Edge  
CS Falling Edge to RD/WR Falling Edge Setup Time  
RD/WR Falling Edge to SCLK Falling Edge Setup  
DIN Setup Time before SCLK Rising Edge  
DIN Hold Time after SCLK Rising Edge  
SCLK Low Pulse Width  
0
10  
10  
40  
40  
0
t9  
SCLK High Pulse Width  
t10  
t11  
t12  
CS Falling Edge to RD/WR Rising Edge Setup Time  
RD/WR Rising Edge to SCLK Falling Edge Setup Time  
DOUT Access Time after RD/WR Rising Edge  
DOUT Access Time after SCLK Falling Edge  
DOUT Bus Relinquish Time after Falling Edge of RD/WR  
DOUT Bus Relinquish Time after Rising Edge of CS  
BUSY Falling Edge to OTI Falling Edge  
RD/WR Rising Edge to OTI Rising Edge  
SCLK Rising Edge to CONVST Falling Edge (Acquisition Time of T/H)  
0
3
20  
20  
30  
30  
150  
40  
400  
3
t13  
3, 4  
t14a  
3, 4  
t14b  
t15  
t16  
t17  
NOTES  
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to  
90% of 5 V) and timed from a voltage level of 1.6 V.  
2See Figures 16, 17, 20 and 21.  
3These figures are measured with the load circuit of Figure 3. They are defined as the time required for DOUT to cross 0.8 V or 2.4 V for VDD = 5 V Ϯ 10% and 0.4 V  
or 2 V for VDD = 3 V Ϯ 10%, as quoted on the specifications page of this data sheet.  
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then  
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus  
relinquish times of the part and as such are independent of external bus loading capacitances.  
Specifications subject to change without notice.  
I
200␮A  
OL  
TO  
OUTPUT  
PIN  
1.6V  
C
L
50pF  
200␮A  
I
OL  
Figure 3. Load Circuit for Access Time and Bus Relinquish Time  
REV. C  
–5–  
12345678...20

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