Datasheet > AD7811_15

AD7811_15

更新时间： 2022-02-26 14:01:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	333K
描述
2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs

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AD7811_15 数据手册

AD7811/AD7812

Test Conditions/Comments

Parameter

Y Version

Unit

POWER SUPPLY

V_DD

2.7

5.5

V min

V max

For Specified Performance

Digital Inputs = 0 V or V_DD

I_DD

Normal Operation

3.5

mA max

Power-Down

Full Power-Down

Partial Power-Down (Internal Ref)

Power Dissipation

350

µA max

See Power-Up Times Section

_DD= 3 V

Normal Operation

10.5

mW max

Auto Full Power-Down

Throughput 1 kSPS

Throughput 10 kSPS

Throughput 100 kSPS

Partial Power-Down (Internal Ref)

Full Power-Down

See Power vs. Throughput Section

31.5

315

3.15

1.05

µW max

mW max

µW max

NOTES

¹See Terminology.

²Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

TIMING CHARACTERISTICS^{1, 2}

(V_DD= 2.7 V to 5.5 V, V_REF= V_DD[EXT] unless otherwise noted)

Parameter

Y Version

Unit

Conditions/Comments

t_POWER-UP

1.5

2.3

µs (max)

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST

Conversion Time

CONVST Pulsewidth

SCLK High Pulsewidth

SCLK Low Pulsewidth

RFS Rising Edge to SCLK Rising Edge Setup Time

TFS Falling Edge to SCLK Falling Edge Setup Time

SCLK Rising Edge to Data Out Valid

DIN Data Valid to SCLK Falling Edge Setup Time

DIN Data Valid after SCLK Falling Edge Hold Time

SCLK Rising Edge to DOUT High Impedance

DOUT High Impedance to CONVST Falling Edge

t₁

t₂

t₃

t₄

t₅

t₆

t₇

100

t₈

t₉

t₁₀

3, 4

t₁₁

NOTES

¹Sample tested to ensure compliance.

²See Figures 16, 17 and 18.

³These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V _DD= 5 V 10% and

0.4 V or 2 V for V_DD= 3 V 10%.

⁴Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t₁₁, quoted in the Timing Characteristics is the true bus relinquish

time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

200␮A

OUTPUT

2.1V

50pF

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

–3–

REV. C

1 234 5 6 7...24

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