AD7745/AD7746
Parameter
Min
Typ
5
Max
Unit
Test Conditions/Comments
Internal reference
Full-Scale Drift vs. Temperature
ppm of FS/°C
0.5
300
±50
80
ꢀ0
75
ppm of FS/°C
External reference
Average VIN Input Current
Analog VIN Input Current Drift
Power Supply Rejection
Power Supply Rejection
Normal Mode Rejection
nA/V
pA/V/°C
dB
dB
dB
Internal reference, VIN = VREF/2
External reference, VIN = VREF/2
50 Hz ± 1%, conversion time = 122.1 ms
90 Hz ± 1%, conversion time = 122.1 ms
VIN = 1 V
50
ꢀ5
dB
dB
Common-Mode Rejection
INTERNAL VOLTAGE REFERENCE
Voltage
1.19ꢀ
1.17
5
1.171
V
TA = 25°C
Drift vs. Temperature
ppm/°C
EXTERNAL VOLTAGE REFERENCE INPUT
Differential REFIN Voltage2
Absolute REFIN Voltage2
Average REFIN Input Current
Average REFIN Input Current Drift
Common-Mode Rejection
0.1
GND − 0.03
2.5
VDD
VDD + 0.03
V
V
±00
±50
80
nA/V
pA/V/°C
dB
SERIAL INTERFACE LOGIC INPUTS
(SCL, SDA)
VIH Input High Voltage
VIL Input Low Voltage
Hysteresis
Input Leakage Current (SCL)
OPEN-DRAIN OUTPUT (SDA)
VOL Output Low Voltage
2.1
V
V
mV
µA
0.8
±1
150
±0.1
0.±
1
V
I
SINK = −9.0 mA
IOH Output High Leakage Current
0.1
µA
VOUT = VDD
RDY
LOGIC OUTPUT (
)
VOL Output Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
VOH Output High Voltage
POWER REQUIREMENTS
VDD-to-GND Voltage
0.±
0.±
V
V
V
V
ISINK = 1.9 mA, VDD = 5 V
ISOURCE = 200 µA, VDD = 5 V
ISINK = 100 µA, VDD = 3 V
ISOURCE = 100 µA, VDD = 3 V
±.0
VDD – 0.9
±.75
2.7
5.25
3.9
850
V
V
µA
µA
µA
µA
VDD = 5 V, nominal
VDD = 3.3 V, nominal
Digital inputs equal to VDD or GND
VDD = 5 V
VDD = 3.3 V
Digital inputs equal to VDD or GND
IDD Current
750
700
0.5
IDD Current Power-Down Mode
2
1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3
Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At
different temperatures, compensation for gain drift over temperature is required.
± The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger
offset can be removed using CAPDACs.
5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
9
The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can
further reduce the CIN offset or the unchanging CIN component.
7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.
8 Using an external temperature sensing diode 2N3ꢀ09, with nonideality factor nf = 1.008, connected as in Figure ±1, with total serial resistance <100 Ω.
ꢀ Full-scale error applies to both positive and negative full scale.
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