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AD7745ARUZ-REEL7 PDF预览

AD7745ARUZ-REEL7

更新时间： 2024-02-26 17:51:05
品牌 Logo 应用领域
亚德诺 - ADI 转换器传感器温度传感器
页数 文件大小 规格书
28页 993K
描述
24-Bit Capacitance-to-Digital Converter with Temperature Sensor

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AD7745ARUZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.48
最大精度（摄氏度）：2 Cel主体宽度：4.4 mm
主体高度：1.2 mm主体长度或直径：5 mm
JESD-609代码：e3安装特点：SURFACE MOUNT
位数：24最大工作电流：0.7 mA
最高工作温度：125 °C最低工作温度：-40 °C
输出接口类型：2-WIRE INTERFACE封装形状/形式：RECTANGULAR
传感器/换能器类型：TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL最大供电电压：5.25 V
最小供电电压：2.7 V表面贴装：YES
端子面层：Matte Tin (Sn)端接类型：SOLDER
Base Number Matches：1

AD7745ARUZ-REEL7 数据手册

 浏览型号AD7745ARUZ-REEL7的Datasheet PDF文件第1页浏览型号AD7745ARUZ-REEL7的Datasheet PDF文件第2页浏览型号AD7745ARUZ-REEL7的Datasheet PDF文件第3页浏览型号AD7745ARUZ-REEL7的Datasheet PDF文件第5页浏览型号AD7745ARUZ-REEL7的Datasheet PDF文件第6页浏览型号AD7745ARUZ-REEL7的Datasheet PDF文件第7页 
AD7745/AD7746  
Parameter  
Min  
Typ  
5
Max  
Unit  
Test Conditions/Comments  
Internal reference  
Full-Scale Drift vs. Temperature  
ppm of FS/°C  
0.5  
300  
±50  
80  
ꢀ0  
75  
ppm of FS/°C  
External reference  
Average VIN Input Current  
Analog VIN Input Current Drift  
Power Supply Rejection  
Power Supply Rejection  
Normal Mode Rejection  
nA/V  
pA/V/°C  
dB  
dB  
dB  
Internal reference, VIN = VREF/2  
External reference, VIN = VREF/2  
50 Hz ± 1%, conversion time = 122.1 ms  
90 Hz ± 1%, conversion time = 122.1 ms  
VIN = 1 V  
50  
ꢀ5  
dB  
dB  
Common-Mode Rejection  
INTERNAL VOLTAGE REFERENCE  
Voltage  
1.19ꢀ  
1.17  
5
1.171  
V
TA = 25°C  
Drift vs. Temperature  
ppm/°C  
EXTERNAL VOLTAGE REFERENCE INPUT  
Differential REFIN Voltage2  
Absolute REFIN Voltage2  
Average REFIN Input Current  
Average REFIN Input Current Drift  
Common-Mode Rejection  
0.1  
GND − 0.03  
2.5  
VDD  
VDD + 0.03  
V
V
±00  
±50  
80  
nA/V  
pA/V/°C  
dB  
SERIAL INTERFACE LOGIC INPUTS  
(SCL, SDA)  
VIH Input High Voltage  
VIL Input Low Voltage  
Hysteresis  
Input Leakage Current (SCL)  
OPEN-DRAIN OUTPUT (SDA)  
VOL Output Low Voltage  
2.1  
V
V
mV  
µA  
0.8  
±1  
150  
±0.1  
0.±  
1
V
I
SINK = −9.0 mA  
IOH Output High Leakage Current  
0.1  
µA  
VOUT = VDD  
RDY  
LOGIC OUTPUT (  
)
VOL Output Low Voltage  
VOH Output High Voltage  
VOL Output Low Voltage  
VOH Output High Voltage  
POWER REQUIREMENTS  
VDD-to-GND Voltage  
0.±  
0.±  
V
V
V
V
ISINK = 1.9 mA, VDD = 5 V  
ISOURCE = 200 µA, VDD = 5 V  
ISINK = 100 µA, VDD = 3 V  
ISOURCE = 100 µA, VDD = 3 V  
±.0  
VDD – 0.9  
±.75  
2.7  
5.25  
3.9  
850  
V
V
µA  
µA  
µA  
µA  
VDD = 5 V, nominal  
VDD = 3.3 V, nominal  
Digital inputs equal to VDD or GND  
VDD = 5 V  
VDD = 3.3 V  
Digital inputs equal to VDD or GND  
IDD Current  
750  
700  
0.5  
IDD Current Power-Down Mode  
2
1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F.  
2 Specification is not production tested, but is supported by characterization data at initial product release.  
3
Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At  
different temperatures, compensation for gain drift over temperature is required.  
± The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register  
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +  
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger  
offset can be removed using CAPDACs.  
5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.  
9
The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can  
further reduce the CIN offset or the unchanging CIN component.  
7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.  
8 Using an external temperature sensing diode 2N3ꢀ09, with nonideality factor nf = 1.008, connected as in Figure ±1, with total serial resistance <100 Ω.  
ꢀ Full-scale error applies to both positive and negative full scale.  
Rev. 0 | Page ± of 28  
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