Preliminary Technical Data
AD7367
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D
A
1
24 DGND
OUT
V
2
D
B
23
22
DRIVE
OUT
DV
3
BUSY
CC
4
21 CNVST
20 SCLK
19 CS
RANGE1
RANGE0
ADDR
AD7367
TOP VIEW
(Not to Scale)
5
6
AGND
7
18 REFSEL
AV
CC
17
16
15
14
13
8
AGND
D
A
D
B
9
CAP
V
CAP
V
10
11
12
SS
DD
V
V
V
A1
B1
B2
V
A2
Figure 2 24-Lead RU-24.
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 23
DOUTA,
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input and 14 SCLK cycles are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
DOUTB
CS
consists of the 14 bits of conversion data and is provided MSB first. If
is held low for a further 14 SCLK
cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data
from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUT
using only one serial port. See the Serial Interface section.
B
2
3
ꢀDRIꢀE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will
operate. This pin should be decoupled to DGND. The voltage range on this pin is 2.7ꢀ to ±.2±ꢀ and may be
different to that at AꢀCC and DꢀCC but should never exceed either by more than 0.3ꢀ To achieve a
throughput rate of 1Msps ꢀDRIꢀE must be greater than or equal to 4.7±ꢀ
DꢀCC
Digital Supply ꢀoltage, 4.7±ꢀ to ±.2±ꢀ. The DꢀCC and AꢀCC voltages should ideally be at the same potential.
For best performance it is recommended that DꢀCC and AꢀCC pins be shorted together, to ensure the voltage
difference between them never exceed 0.3 ꢀ even on a transient basis. This supply should be decoupled to
DGND. 10 µF and 100 nF decoupling capacitors should be placed on the DꢀCC pin.
4,±
6
RANGE0,
RANGE1
Analog Input Range Selection. Logic inputs. The polarity on these pins determines the input range of the
analog input channels. See Analog Inputs section and Table 7 for details
ADDR
Multiplexer Select. Logic input. This input is used to select the pair of channels to be simultaneously
converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic
state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
7,17
8
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7367. All analog input signals and
any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and
must not be more than 0.3 ꢀ apart, even on a transient basis.
Analog Supply ꢀoltage, 4.7± ꢀ to ±.2± ꢀ. This is the supply voltage for the ADC cores. The AꢀCC and DꢀCC
voltages ideally should be at the same potential. For best performance it is recommended that DꢀCC and
AꢀCC pins be shorted together, to ensure the voltage difference between them never exceed 0.3 ꢀ even on a
transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF decoupling capacitors should
be placed on the AꢀCC pins.
AꢀCC
9,16
DCAPA,
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference
buffer for each respective ADC. For best performance it is recommended to use 680nF decoupling capacitor
on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and
Rev. PrD | Page 7 of 16
DCAPB
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