Preliminary Technical Data
AD7356
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
INA+
DRIVE
V
SCLK
SDATA
SDATA
DGND
AGND
CS
INA-
REF
A
A
B
AD7356
TOP VIEW
(Not to Scale)
REFGND
AGND
REF
B
V
INB-
V
V
INB+
DD
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
9
VDD
Power Supply Input. The VDD range for the AD7356 is 2.5V +/- 5ꢀ. The supply should be decoupled to AGND
with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
16
VDRIVE
CS
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will
operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7356 and framing the serial data transfer.
10
SCLK
15
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7356. This
clock is also used as the clock source for the conversion process.
SDATAA,
SDATAB
14,13
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. 14 SCLK falling edges are required to access the 12 bits of data from the
AD7356. The data simultaneously appears on both data output pins from the simultaneous conversions of
both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data
is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7356, then two trailing zeros
will appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATAA or SDATAB ,
the data from the other ADC follows on the SDATA pin. This allows data from a simultaneous conversion on
both ADCs to be gathered in serial format on either SDATAA or SDATAB using only one serial port.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7356. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
5, 11
4
AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7356. All analog input
signals and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.
Reference Ground. This is the ground reference point for the reference circuitry on the AD7356 Any external
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between
this pin and the REFA and REFB pins.
Reference decoupling capacitor pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple the
each reference pin with a 10µF capacitor. Provided the output is buffered, the on-chip reference can be taken
from these pins and applied externally to the rest of the system. The nominal internal reference voltage is
2.048V and this appears at these pins. These pins can also be overdriven by an external reference. The input
voltage range for the external reference is 2.048+100mV to Vdd.
REFGND
REFA, REFB
3, 6
1, 2
7, 8
VINA+, VINA-
VINB+, VINB-
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
Rev. PrC | Page 7 of 18
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