Datasheet > AD7356YRUZ-500RL7

AD7356YRUZ-500RL7

更新时间： 2024-02-16 18:41:48

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
18页	192K
描述
Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC

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AD7356YRUZ-500RL7 数据手册

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Preliminary Technical Data

AD7356

TIMING SPECIFICATIONS

V_DD= 2.5 V, V_DRIVE= 2.5 V to 3.3 V, internal reference = 2.048 V, T_A= T_MAXto T_MIN¹, unless otherwise noted.

Table 2.

Parameter

Limit at T_MIN, T_MAX

Unit

Description

f_SCLK

kHz min

MHz max

ns max

ns min

ns max

ns min

ns max

ns min

ns max

t_CONVERT

t_QUIET

t₂

t₂+13 × t_SCLK

AD7356, 12 bit resolution, t_SCLK= 1/f_SCLK

Minimum time between end of serial read and next falling edge of

to SCLK setup time

t₃

TBD

Delay from until D_OUTA and D_OUTB are three-state disabled

Data access time after SCLK falling edge

SCLK low pulse width

t₄

TBD

t₅

t₆

t₇

t₈

t₉

t₁₀

0.40 t_SCLK

TBD

SCLK high pulse width

SCLK to data valid hold time

TBD

rising edge to D_OUTA, D_OUTB, high impedance

rising edge to falling edge pulse width

TBD

SCLK falling edge to D_OUTA, D_OUTB, high impedance

Latency

No Latency

¹Temperature ranges are as follows: Y Grade: −40ꢁC to +125ꢁC, B Grade: −40ꢁC to +85ꢁC.

²The time required for the output to cross 0.4 V or 2.4 V.

Rev. PrC | Page 5 of 18

1 2 3 456 7 8...18

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