(AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; DGND = AGND = 0 V, fDMCLK
16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
=
AD73322–SPECIFICATIONS1
AD73322A
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
REFERENCE
REFCAP
5VEN = 0
Absolute Voltage, VREFCAP
REFCAP TC
1.08
1.2
50
1.32
V
ppm/°C 0.1 µF Capacitor Required from
REFOUT
REFCAP to AGND2
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
130
1.2
Ω
V
kΩ
pF
1.08
1
1.32
100
Unloaded
INPUT AMPLIFIER
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
±1.0
1.578
50
mV
V
Ω
Max Output Swing = (1.578/1.2) × VREFCAP
fC = 32 kHz
100
pF
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
+1
–1
5
±1.0
1.0
0.5
Bits
%
µs
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
Delay
µs
ADC SPECIFICATIONS
5VEN = 0
Maximum Input Range at VIN2, 3
1.578
–2.85
1.0954
–6.02
V p-p
dBm
V p-p
dBm
Measured Differentially
Max Input = (1.578/1.2) × VREFCAP
Measured Differentially
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
–0.5
–1.5
0.4
–0.7
±0.1
+1.2
+0.1
dB
dB
dB
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 5
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 8 kHz
0 Hz to fSAMP/2; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
72
78
78
57
56
dB
dB
dB
dB
55
52
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
–84
–70
–65
–71
–100
–73
–60
dB
dB
dB
dBm0
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
Crosstalk
ADC-to-DAC
ADC-to-ADC
–100
dB
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
–70
+10
–65
dB
mV
dB
DC Offset
–30
+45
Power Supply Rejection
Group Delay4, 5
25
20
µs
kΩ
Input Resistance at PGA2, 4, 6
Input Amplifiers Bypassed
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
+1
–1
16
Bits
µs
Tested to 5 MSBs of Settings
Includes DAC Delay
Delay
25
Settling Time
100
µs
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
–2–
REV. B