Datasheet > AD7292

AD7292

更新时间： 2022-02-26 12:08:25

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
41页	734K
描述
10-Bit Monitor and Control System with ADC,DACs, Temperature Sensor, and GPIOs

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AD7292 数据手册

AD7292

Data Sheet

TIMING SPECIFICATIONS

AV_DD= 4.75 V to 5.25 V, DV_DD= 1.8 V to 5.25 V, V_REF= 1.25 V internal, V_DRIVE= 1.8 V to 5.25 V, A_GND= 0 V, C_L= 27 pF, T_A= −40°C

to +125°C, unless otherwise noted.¹

Table 5.

Limit at T_MIN/T_MAX

Parameter

Description

V_DRIVE= 1.8 V

V_DRIVE= 2.7 V to 5.25 V

Unit

t_CONVERT

ADC conversion time/BUSY high time

Temperature sensor disabled

Temperature sensor enabled

ADC acquisition time

950

5.85

950

5.85

ns max

μs max

ns max

MHz max

ns min

ns max

ns min

ns max

ns min

ns max

t_ACQ

f_SCLK

t₁

Frequency of serial read clock²

SCLK period

t₂

t₃

t₄

SCLK low

SCLK high

CS falling edge to SCLK rising edge

DIN setup time to SCLK falling edge

DIN hold time after SCLK falling edge

SCLK falling edge to CS rising edge

CS high

t₅

t₆

t₇

t₈

t₉

t₁₀

t₁₁

SCLK to output data valid delay time

SCLK to output data valid hold time

CS rising edge to SCLK rising edge

CS rising edge to DOUT high impedance

t₁₂

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DRIVE).

²For V_DRIVE= 2.5 V, f_SCLK= 22 MHz maximum.

³Time required for the output to cross 0.2 × V_DRIVEand 0.8 × V_DRIVEwhen V_DRIVE= 1.8 V; time required for the output to cross 0.3 × V_DRIVEand 0.7 × V_DRIVEwhen V_DRIVE= 2.7 V to 5.25 V.

⁴Guaranteed by design.

Timing Diagram

BUSY

t₇

t₈

t₃

t₁₁

t₂

t₁

t₄

SCLK

DIN

t₅

t₆

LSB

t₁₀

HIGH-Z

t₁₂

LSB

DOUT

t₉

PROVIDED THE READ BIT IS SET.

IF AN ADC CONVERSION IS REQUESTED.

t₇= 5ns IF NO ADC CONVERSION

955ns WITH ADC CONVERSION

Figure 2. Serial Interface Timing Diagram

Rev. A | Page 6 of 40

1...4 5 678 9 10...41

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