Datasheet > AD7177-2_17

AD7177-2_17

更新时间： 2024-02-09 13:27:50

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
61页	988K
描述
32-Bit, 10 kSPS, Sigma-Delta ADC with Settling and True Rail-to-Rail Buffers

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AD7177-2_17 数据手册

AD7177-2

Data Sheet

SPECIFICATIONS

AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,

internal master clock (MCLK) = 16 MHz, T_A= T_MINto T_MAX(−40°C to +105°C), unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC SPEED AND PERFORMANCE

Output Data Rate (ODR)

No Missing Codes¹

Resolution

Noise

FIR Filter Rejection

ACCURACY

10,000

SPS

Bits

See Table 19 to Table 23

See Table 23

Integral Nonlinearity (INL)

All input buffers disabled

All input buffers enabled

Internal short

All input buffers disabled

All input buffers enabled

3.5

7.8

ppm of FSR

µV

3.5

2.5

0.4

Offset Error²

Offset Drift

Gain Error²

nV/°C

100

0.75

ppm of FSR

ppm/°C

Gain Drift

REJECTION

Power Supply Rejection

Common-Mode Rejection

At DC

AVDD1, AVDD2, V_IN= 1 V

V_IN= 0.1 V

120

At 50 Hz, 60 Hz¹

20 Hz output data rate (post filter),

50 Hz 1 Hz and 60 Hz 1 Hz

Normal Mode Rejection¹

Internal clock, 20 SPS ODR (postfilter)

External clock, 20 SPS ODR (postfilter)

ANALOG INPUTS

Differential Input Range

Absolute Voltage Limits¹

Input Buffers Disabled

Input Buffers Enabled

Analog Input Current

Input Buffers Disabled

Input Current

V_REF= (REF+) − (REF−)

V_REF

AVSS − 0.05

AVSS

AVDD1 + 0.05

AVDD1

0.75

µA/V

nA/V/°C

Input Current Drift

External clock

Internal clock ( 2.5% clock)

Input Buffers Enabled

Input Current

Input Current Drift

AVDD1 − 0.2 V to AVSS + 0.2 V

AVDD1 to AVSS

1 kHz input

pA/°C

nA/°C

Crosstalk

−120

INTERNAL REFERENCE

Output Voltage

100 nF external capacitor to AVSS

REFOUT, with respect to AVSS

REFOUT, T_A= 25°C

2.5

Initial Accuracy³

−0.12

−10

+0.12

% of V

Temperature Coefficient¹

0°C to 105°C

−40°C to +105°C

Reference Load Current, I_LOAD

Power Supply Rejection

Load Regulation

+10

ppm/°C

ppm/mA

AVDD1, AVDD2 (line regulation)

∆V_OUT/∆I_LOAD

Rev. B | Page 4 of 60

1 2 3 456 7 8...61

中文翻译

下载PDF

与AD7177-2_17相关器件

型号	品牌	获取价格	描述	数据表
AD7177-2BRUZ	ADI	获取价格	32-Bit, 10 kSPS, Sigma-Delta ADC with 100 &am
AD7177-2BRUZ-RL7	ADI	获取价格	32-Bit, 10 kSPS, Sigma-Delta ADC with 100 &am
AD7183	ADI	获取价格	Advanced Video Decoder with 10-Bit ADC and Component Input Support
AD7190	ADI	获取价格	4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
AD7190_08	ADI	获取价格	4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
AD7190BRUZ	ADI	获取价格	4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
AD7190BRUZ-REEL	ADI	获取价格	4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
AD7190WBRUZ	ADI	获取价格	4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
AD7190WBRUZ-RL	ADI	获取价格	1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24, ROHS COMPLIANT, TSSOP-24
AD7191	ADI	获取价格	Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors

与AD7177-2_17相关文章

LM317T数据手册解读：产品特性、应用、封装与引脚详解
2024-06-14

5
一文带你了解?DB3二极管好坏判断、参数信息、替代推荐
2024-06-14

10
LM358DR数据手册：引脚说明、电气参数及替换型号推荐
2024-06-14

4
OP07CP数据手册解读：引脚信息、电子参数
2024-06-14

4

产品中心

服务支持

精选活动

关于我们

帮助中心

AD7177-2_17

AD7177-2_17 数据手册

与AD7177-2_17相关器件

与AD7177-2_17相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD7177-2_17

AD7177-2_17 数据手册

与AD7177-2_17相关器件

与AD7177-2_17相关文章

您还可以找

您在本页遇到什么问题？