AD671–SPECIFICATIONS
MIN to TMAX, with VCC = +5 V
5%, VREF = +5.000 V, unless otherwise noted)
؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V
DIGITAL SPECIFICATIONS (؎For all grades T
LOGIC INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = VLOGIC
Low Level Input Current (VIN = 0 V)
Input Capacitance
VIH
VIL
IIH
IIL
V
V
µA
µA
pF
)
CIN
5
5
LOGIC OUTPUTS
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Output Capacitance
VOH
VOL
COUT
V
V
pF
Specifications shown in
are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
MIN to TMAX with VCC = +5 V
؎ 5%, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
؎
5%, VLOGIC = +5 V
؎
10%, VEE = –5 V
SWITCHING SPECIFICATIONS (For all grades T
Conversion Time
(AD671-500)
(AD671-750)
tC
tC
475
725
ns
ns
ENCODE Pulse Width High
(AD671-500)
(AD671-750)
ENCODE Pulse Width Low
DAV Pulse Width
tENC
tENC
tENCL
20
20
20
30
50
ns
ns
ns
(AD671-500)
(AD671-750)
ENCODE Falling Edge Delay
Start New Conversion Delay
Data and OTR Delay from DAV Falling Edge
Data and OTR Valid before DAV Rising Edge
tDAV
tDAV
tF
75
75
0
0
20
20
200
300
ns
ns
ns
ns
ns
ns
tR
tDD
1
75
75
2
tSS
NOTES
1tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.
2tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
b. Encode Pulse LOW
a. Encode Pulse HIGH
Figure 1. AD671 Timing Diagrams
REV. B
–4–