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AD6652BBCZ PDF预览

AD6652BBCZ

更新时间: 2024-01-31 12:11:31
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亚德诺 - ADI 接收机
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76页 2300K
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AD6652BBCZ 数据手册

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12-Bit, 65 MSPS  
IF to Baseband Diversity Receiver  
AD6652  
FEATURES  
APPLICATIONS  
SNR = 90 dB in 150 kHz bandwidth (to Nyquist  
@ 61.44 MSPS)  
Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)  
Integrated dual-channel ADC:  
Communications  
Diversity radio systems  
Multimode digital receivers:  
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,  
IS95, IS136, CDMA2000, IMT-2000  
Sample rates up to 65 MSPS  
IF sampling frequencies to 200 MHz  
Internal ADC voltage reference  
I/Q demodulation systems  
Smart antenna systems  
Integrated ADC sample-and-hold inputs  
Flexible analog input range (1 V to 2 V p-p)  
Differential analog inputs  
General-purpose software radios  
Broadband data applications  
Instrumentation and test equipment  
ADC clock duty cycle stabilizer  
85 dB channel isolation/crosstalk  
Integrated wideband digital downconverter (DDC):  
Crossbar switched DDC inputs  
Digital resampling for noninteger decimation  
Programmable decimating FIR filters  
Flexible control for multicarrier and phased array  
Dual AGC stages for output level control  
Dual 16-bit parallel or 8-bit link output ports  
User-configurable built-in self-test (BIST) capability  
Energy-saving power-down modes  
FUNCTIONAL BLOCK DIAGRAM  
DUAL-CHANNEL 12-BIT A/D FRONT END  
WIDEBAND DIGITAL DOWNCONVERTER (DDC)  
RAM  
COEF.  
FILTER  
PORT A  
RCIC2  
RESAMPLER  
TO OUTPUT PORTS  
VINA+  
CIC5  
12  
/
ADC  
CHANNEL  
A
CHANNEL A  
SHA  
8-BIT DSP  
LINK  
VINA–  
RCF OUTPUTS  
CHANNELS 0, 1, 2, 3  
CHANNEL 0  
OTRA  
LIA  
LIA  
NCO  
NCO  
OR  
REFTA  
REFBA  
RAM  
COEF.  
FILTER  
16-BIT  
PARALLEL  
OUTPUT  
RCIC2  
RESAMPLER  
TO OUTPUT PORTS  
AGC A*  
CIC5  
PSEUDO  
RANDOM  
NOISE  
VREF  
SENSE  
CHANNEL 1  
VREF  
CONTROL  
SEQUENCE  
OUTPUT  
MUX  
CIRCUITRY  
RAM  
COEF.  
FILTER  
REFTB  
REFBB  
RCIC2  
RESAMPLER  
TO OUTPUT  
PORTS  
CIC5  
CIC5  
LIB  
LIB  
PORT B  
CHANNEL 2  
OTRB  
NCO  
NCO  
AGC B*  
VINB+  
VINB–  
12  
ADC  
CHANNEL  
B
8-BIT DSP  
LINK  
SHA  
/
RAM  
COEF.  
FILTER  
CHANNEL B  
RCIC2  
RESAMPLER  
TO OUTPUT PORTS  
OR  
RCF OUTPUTS  
CHANNELS 0, 1, 2, 3  
16-BIT  
PARALLEL  
OUTPUT  
CHANNEL 3  
*DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL  
CLOCK  
DUTY  
CYCLE  
SYNCA  
SYNCB  
SYNCC  
SYNCD  
EXTERNAL  
SYNC.  
CIRCUIT  
PDWN  
BUILT-IN  
SELF-TEST  
CIRCUITRY  
MODE  
SELECT  
ACLK  
DDC  
CLK  
PROGRAM  
MICROPORT  
SHRDREF  
DUTYEN  
STABILIZER  
8
3
3
+3.0AVDD  
+3.3VDDIO  
2.5VDD  
AGND  
DGND  
CLK  
DATA CONT ADD  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
 

AD6652BBCZ 替代型号

型号 品牌 替代类型 描述 数据表
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完全替代

12-Bit, 65 MSPS IF to Baseband Diversity Receiver

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