AD6644
DIGITAL SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN = −25°C, TMAX = +85°C, unless otherwise noted.
Table 2.
AD6644AST-40
AD6644AST-65
Parameter
Temp
Test Level1
Unit
Min
Typ
Max
Min
Typ
Max
ENCODE
ENCODE INPUTS (ENCODE,
)
Differential Input Voltage2
Differential Input Resistance
Differential Input Capacitance
Full
25°C
25°C
IV
V
V
0.4
0.4
V p-p
kΩ
pF
10
2.5
10
2.5
LOGIC OUTPUTS (D13 to D0, DRY, OVR)
Logic Compatibility
Logic 1 Voltage3
CMOS
2.5
0.4
CMOS
2.5
0.4
Full
Full
V
V
V
V
Logic 0 Voltage3
Output Coding
DMID
Twos complement
DVCC/2
Twos complement
DVCC/2
Full
V
V
1 See the Explanation of Test Levels section.
2
ENCODE
All ac specifications tested by driving ENCODE and
differentially. Reference Figure 18 for performance vs. encode power.
3 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrade performance.
SWITCHING SPECIFICATIONS
ENCODE
AVCC = 5 V, DVCC = 3.3 V; ENCODE and
= maximum conversion rate MSPS; TMIN = –25°C, TMAX = +85°C, unless otherwise noted.
Table 3.
AD6644AST-40
Typ Max
AD6644AST-65
Typ Max
Parameter
Temp
Full
Full
Full
Full
Test Level1
Unit
MSPS
MSPS
ns
Min
Min
Maximum Conversion Rate
Minimum Conversion Rate
ENCODE Pulse Width High
ENCODE Pulse Width Low
II
40
65
IV
IV
IV
15
15
10
10
6.5
6.5
ns
1 See the Explanation of Test Levels section.
ENCODE
AVCC = 5 V, DVCC = 3.3 V; ENCODE and
unless otherwise noted.
= maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, CLOAD = 10 Pf,
Table 4.
AD6644AST-40/65
Parameter
ENCODE INPUT PARAMETERS2
Name
Temp
Test Level1
Unit
Min
Typ
Max
Encode Period @ 65 MSPS
Encode Period @ 40 MSPS
Encode Pulse Width High3 @ 65 MSPS
Encode Pulse Width Low @ 65 MSPS
ENCODE/DATA READY
tENC
tENC
tENCH
tENCL
Full
Full
Full
Full
V
V
IV
IV
15.4
25
7.7
7.7
ns
ns
ns
ns
6.2
6.2
9.2
9.2
Encode Rising to Data Ready Falling
Encode Rising to Data Ready Rising
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
ENCODE/DATA (D13:0), OVR
ENCODE to DATA Falling Low
ENCODE to DATA Rising Low
ENCODE to DATA Delay (Hold Time)4
ENCODE to DATA Delay (Setup Time)5
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
tDR
tE_DR
Full
IV
2.6
3.4
tENCH + tDR
11.1
4.6
ns
Full
Full
IV
IV
10.3
15.1
12.3
17.1
ns
ns
15.9
tE_FL
tE_RL
tH_E
tS_E
Full
Full
Full
IV
IV
IV
3.8
3.0
3.0
5.5
4.3
4.3
9.2
6.4
6.4
ns
ns
ns
tENC − tE_FL
9.8
19.4
Full
Full
IV
IV
6.2
15.9
11.6
21.2
ns
ns
Rev. D | Page 4 of 24