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AD6623

更新时间： 2024-02-15 06:12:38
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 374K
描述
4-Channel, 104 MSPS Digital Transmit Signal Processor TSP

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AD6623 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：FQFP,针数：128
Reach Compliance Code：unknown风险等级：5.1
JESD-30 代码：R-PQFP-G128JESD-609代码：e3
长度：20 mm湿度敏感等级：3
功能数量：1端子数量：128
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装形状：RECTANGULAR封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
座面最大高度：3.4 mm标称供电电压：2.5 V
表面贴装：YES技术：CMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
Base Number Matches：1

AD6623 数据手册

 浏览型号AD6623的Datasheet PDF文件第2页浏览型号AD6623的Datasheet PDF文件第3页浏览型号AD6623的Datasheet PDF文件第4页浏览型号AD6623的Datasheet PDF文件第5页浏览型号AD6623的Datasheet PDF文件第6页浏览型号AD6623的Datasheet PDF文件第7页 
4-Channel, 104 MSPS Digital  
Transmit Signal Processor (TSP)  
a
AD6623  
Digital Resampling for Noninteger Interpolation Rates  
NCO Frequency Translation  
FEATURES  
Pin Compatible to the AD6622  
18-Bit Parallel Digital IF Output  
Real or Interleaved Complex  
Spurious Performance Better than –100 dBc  
Separate 3-Wire Serial Data Input for Each Channel  
Bidirectional Serial Clocks and Frames  
Microprocessor Control  
2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs  
JTAG Boundary Scan  
18-Bit Bidirectional Parallel Digital IF Input/Output  
Allows Cascade of Chips for Additional Channels  
Clipped or Wrapped Over Range  
Two’s Complement or Offset Binary Output  
Four Independent Digital Transmitters in Single Package  
RAM Coefficient Filter (RCF)  
Programmable IF and Modulation for Each Channel  
Programmable Interpolating RAM Coefficient Filter  
p/4-DQPSK Differential Phase Encoder  
3p/8-PSK Linear Encoder  
APPLICATIONS  
Cellular/PCS Base Stations  
Micro/Pico Cell Base Stations  
Wireless Local Loop Base Stations  
Multicarrier, Multimode Digital Transmit  
GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS,  
CDMA2000  
Phased Array Beam Forming Antennas  
Software Defined Radio  
Tuning Resolution Better than 0.025 Hz  
Real or Complex Outputs  
8-PSK Linear Encoder  
Programmable GMSK Look-Up Table  
Programmable QPSK Look-Up Table  
All-Pass Phase Equalizer  
Programmable Fine Scaler  
Programmable Power Ramp Unit  
High Speed CIC Interpolating Filter  
FUNCTIONAL BLOCK DIAGRAM  
NCO = NUMERICALLY CONTROLLED  
OSCILLATOR/TUNER  
SDINA  
QIN  
I
I
I
I
RAM  
COEFFICIENT  
FILTER  
SCALER  
AND  
POWER  
RAMP  
DATA  
DATA  
CHAN A  
NCO  
CIC5  
RCIC2  
SDFIA  
SDFOA  
SCLKA  
SP  
SP  
Q
Q
Q
Q
ORT  
ORT  
IN  
[17–0]  
FILTER  
FILTER  
SDINB  
SDFIB  
I
I
I
I
RAM  
COEFFICIENT  
FILTER  
SCALER  
AND  
POWER  
RAMP  
CHAN B  
NCO  
CIC5  
FILTER  
RCIC2  
FILTER  
Q
Q
Q
Q
SYNC  
SDFOB  
SCLKB  
4
SUMMATION  
SDINC  
SDFIC  
I
I
I
I
RAM  
COEFFICIENT  
FILTER  
SCALER  
AND  
POWER  
RAMP  
DATA  
DATA  
CHAN C  
CHAN D  
CIC5  
RCIC2  
NCO  
NCO  
SP  
SP  
Q
Q
Q
Q
ORT  
ORT  
FILTER  
FILTER  
SDFOC  
SCLKC  
OEN  
SDIND  
SDFID  
I
I
I
I
RAM  
COEFFICIENT  
FILTER  
SCALER  
AND  
POWER  
RAMP  
QOUT  
CIC5  
FILTER  
RCIC2  
FILTER  
Q
Q
Q
Q
OUT  
[17:0]  
SDFOD  
SCLKD  
JTAG  
MICROPORT  
TDL TDO TMS TCK TRST  
D[7:0]  
DS DTACK RW MODE A[2:0]  
CS  
CLK  
RESET  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  
1234567...40

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