AD652JP

更新时间： 2024-02-01 20:01:24

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
16页	951K
描述
Monolithic Synchronous Voltage-to-Frequency Converter

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技术参数
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AD652JP 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	CERDIP-16	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.65
Is Samacsys：	N	转换器类型：	VOLTAGE TO FREQUENCY CONVERTER
JESD-30 代码：	R-GDIP-T16	JESD-609代码：	e0
长度：	19.05 mm	最大线性误差 (EL)：	0.05%
湿度敏感等级：	NOT APPLICABLE	最大负输入电压：	-5 V
最大负电源电压：	-18 V	最小负电源电压：	-6 V
标称负供电电压：	-15 V	功能数量：	1
端子数量：	16	最大工作频率：	4 MHz
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE	最大正输入电压：	5 V
认证状态：	COMMERCIAL	座面最大高度：	5.08 mm
最大供电电压：	18 V	最小供电电压：	6 V
标称供电电压：	15 V	表面贴装：	NO
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
最大总误差：	0.5%	宽度：	7.62 mm
Base Number Matches：	1

AD652JP 数据手册

AD652

ORDERING GUIDE

Specified

Gain

Drift

Part

ppm/؇C 1 MHz

Temperature Package

Number¹100 kHz Linearity % Range ؇C

Options²

AD652JP

50 max

0.02 max

0.005 max

0.02 max

0.005 max

0.02 max

0 to +70

–40 to +85

–55 to +125

PLCC (P-20A)

Cerdip (Q-16)

AD652KP 25 max

AD652AQ 50 max

AD652BQ 25 max

AD652SQ 50 max

NOTES

¹For details on grade and package offerings screened in accordance with MIL-

STD-883, refer to the Analog Devices Military Products Databook or current

AD652/883 data sheet.

²P = Plastic Leaded Chip Carrier; Q = Cerdip.

Figure 1a. Cerdip Pin Configuration

PIN CONFIGURATIONS

The pinouts of the AD652 SVFC are shown in Figure 1. A

block diagram of the device configured as a SVFC, along with

various system waveforms, is shown in Figure 2.

Q-16 PACKAGE

P-20A PACKAGE

+V_S

TRIM

+V_S

OP AMP OUT

OP AMP “—”

OP AMP “+”

10 VOLT INPUT

–V_S

OP AMP OUT

OP AMP “—”

OP AMP “+”

5 VOLT INPUT

10 VOLT INPUT

8 VOLT INPUT

OPTIONAL 10 V INPUT

–V_S

C_OS

CLOCK INPUT

FREQ OUT

DIGITAL GND

ANALOG GND

COMP “—”

COMP “+“

COMP REF

C_OS

CLOCK INPUT

FREQ OUT

DIGITAL GROUND

ANALOG GND

COMP “—”

COMP “+”

COMP REF

THEORY OF OPERATION

A synchronous VFC is similar to other voltage-to-frequency

converters in that an integrator is used to perform a charge-

balance of the input signal with an internal reference current.

However, rather than using a one-shot as the primary timing

element which requires a high quality and low drift capacitor,

a synchronous voltage-to-frequency converter (SVFC) uses an

external clock; this allows the designer to determine the system

stability and drift based upon the external clock selected. A crys-

tal oscillator may also be used if desired.

Figure 1b. PLCC Pin Configuration

Figure 2 shows the typical up-and-down ramp integrator output

of a charge-balance VFC. After the integrator output has crossed

the comparator threshold and the output of the AND gate has

gone high, nothing happens until a negative edge of the clock

comes along to transfer the information to the output of the

D-FLOP. At this point, the clock level is low, so the latch does

not change state. When the clock returns high, the latch output

goes high and drives the switch to reset the integrator. At the

same time the latch drives the AND gate to a low output state.

On the very next negative edge of the clock the low output state

of the AND gate is transferred to the output of the D-FLOP

and then when the clock returns high, the latch output goes low

and drives the switch back into the Integrate Mode. At the same

time the latch drives the AND gate to a mode where it will truth-

fully relay the information presented to it by the comparator.

The SVFC architecture provides other system advantages besides

low drift. If the output frequency is measured by counting

pulses gated to a signal which is derived from the clock, the

clock stability is unimportant and the device simply performs as a

voltage controlled frequency divider, producing a high resolution

A/D. If a large number of inputs must be monitored simulta-

neously in a system, the controlled timing relationship between

the frequency output pulses and the user supplied clock greatly

simplifies this signal acquisition. Also, if the clock signal is pro-

vided by a VFC, then the output frequency of the SVFC will be

proportional to the product of the two input voltages.

Since the reset pulses applied to the integrator are exactly one

clock period long, the only place where drift can occur is in a

variation of the symmetry of the switching speed with tempera-

ture. Since each reset pulse is identical to every other, the AD652

SVFC produces a very linear voltage to frequency transfer rela-

tion. Also, since all of the reset pulses are gated by the clock,

Hence, multiplication and A-to-D conversion on two signals are

performed simultaneously.

–4–

REV. B

1 2 345 6 7...16

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