Datasheet > AD652BQ

AD652BQ

更新时间： 2024-01-19 00:03:46

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		转换器
页数	文件大小	规格书
29页	1796K
描述
VOLTAGE-FREQUENCY CONVERTER, 4MHz, CDIP16, CERDIP-16

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AD652BQ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	CERDIP-16	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.65
转换器类型：	VOLTAGE TO FREQUENCY CONVERTER	JESD-30 代码：	R-GDIP-T16
JESD-609代码：	e0	长度：	19.05 mm
最大线性误差 (EL)：	0.02%	湿度敏感等级：	NOT APPLICABLE
最大负输入电压：	-5 V	最大负电源电压：	-18 V
最小负电源电压：	-6 V	标称负供电电压：	-15 V
功能数量：	1	端子数量：	16
最大工作频率：	4 MHz	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
最大正输入电压：	5 V	认证状态：	COMMERCIAL
座面最大高度：	5.08 mm	最大供电电压：	18 V
最小供电电压：	6 V	标称供电电压：	15 V
表面贴装：	NO	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT APPLICABLE	最大总误差：	0.5%
宽度：	7.62 mm	Base Number Matches：	1

AD652BQ 数据手册

AD652

THEORY OF OPERATION

A synchronous VFC is similar to other voltage-to-frequency

converters in that an integrator is used to perform a charge-

balance of the input signal with an internal reference current.

However, rather than using a one-shot as the primary timing

element, which requires a high quality and low drift capacitor, a

synchronous voltage-to-frequency converter (SVFC) uses an

external clock. This allows the designer to determine the system

stability and drift based upon the external clock selected. A

crystal oscillator may also be used if desired.

AD652

SYNCHRONOUS

VOLTAGE-TO-FREQUENCY

CONVERTER

REFERENCE

OP AMP OUT

OP AMP "–"

OP AMP "+"

5V INPUT

18 COMP "+"

17 COMP "–"

"D"

FLOP

16 ANALOG GND

15 DIGITAL GND

14 FREQ OUT

AND

The SVFC architecture provides other system advantages

besides low drift. If the output frequency is measured by

counting pulses gated to a signal that is derived from the clock,

the clock stability is unimportant and the device simply

performs as a voltage-controlled frequency divider, producing a

high resolution A/D. If a large number of inputs must be

monitored simultaneously in a system, the controlled timing

relationship between the frequency output pulses and the user-

supplied clock greatly simplifies this signal acquisition. Also, if

the clock signal is provided by a VFC, the output frequency of

the SVFC is proportional to the product of the two input

voltages. Therefore, multiplication and A-to-D conversion on

two signals are performed simultaneously.

10kΩ

ONE

SHOT

1mA

16kΩ

10V INPUT

4kΩ

NC = NO CONNECT

Figure 3. PLCC Pin Configuration

Figure 4 shows the typical up-and-down ramp integrator output

of a charge-balance VFC. After the integrator output has

crossed the comparator threshold and the output of the AND

gate has gone high, nothing happens until a negative edge of the

clock comes along to transfer the information to the output of

the D FLOP. At this point, the clock level is low, so the latch does

not change state. When the clock returns high, the latch output

goes high and drives the switch to reset the integrator; at the

same time, the latch drives the AND gate to a low output state.

On the very next negative edge of the clock, the low output state

of the AND gate is transferred to the output of the D FLOP.

When the clock returns high, the latch output goes low and

drives the switch back into the Integrate mode. At the same

time, the latch drives the AND gate to a mode where it

truthfully relays the information presented to it by the

comparator.

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

16 COMP REF

15 COMP "+"

REFERENCE

TRIM

14 COMP "–"

OP AMP OUT

OP AMP "–"

OP AMP "+"

10 VOLT INPUT

13 ANALOG GND

12 DIGITAL GND

11 FREQ OUT

10 CLOCK INPUT

ONE

SHOT

20kΩ

1mA

–V

AND

"D"

FLOP

Figure 2. CERDIP Pin Configuration

The pinouts of the AD652 SVFC are shown in Figure 2 and

Figure 3. A block diagram of the device configured as an SVFC,

along with various system waveforms, is shown in Figure 4.

Because the reset pulses applied to the integrator are exactly one

clock period long, the only place where drift can occur is in a

variation of the symmetry of the switching speed with

temperature.

Since each reset pulse is identical, the AD652 SVFC produces a

very linear voltage-to-frequency transfer relation. Also, because

all reset pulses are gated by the clock, there are no problems

with dielectric absorption causing the duration of a reset pulse

to be influenced by the length of time since the last reset.

Rev. C | Page 6 of 28

1...4 5 678 9 10...29

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与AD652BQ相关器件

型号	品牌	描述	获取价格	数据表
AD652BQ/+	ADI	IC VOLTAGE-FREQUENCY CONVERTER, 4 MHz, CDIP16, CERDIP-16, Analog Special Function Converte	获取价格
AD652BQ2	ADI	Monolithic Synchronous Voltage-to-Frequency Converter	获取价格
AD652JP	ADI	Monolithic Synchronous Voltage-to-Frequency Converter	获取价格
AD652JP-REEL	ADI	Monolithic Synchronous Voltage-to-Frequency Converter	获取价格
AD652JP-REEL	ROCHESTER	VOLTAGE-FREQUENCY CONVERTER, 4 MHz, PQCC20, PLASTIC, LCC-20	获取价格
AD652JP-REEL7	ADI	Monolithic Synchronous Voltage-to-Frequency Converter	获取价格

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