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AD630J

更新时间： 2024-02-16 02:59:38
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 289K
描述
Balanced Modulator/Demodulator

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AD630J 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：CERAMIC, LCC-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：5A991.AHTS代码：8542.39.00.01
风险等级：5.02Is Samacsys：N
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-CQCC-N20
JESD-609代码：e0长度：8.89 mm
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：2.54 mm
最大压摆率：5 mA最大供电电压 (Vsup)：16.5 V
最小供电电压 (Vsup)：5 V表面贴装：YES
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：8.89 mmBase Number Matches：1

AD630J 数据手册

 浏览型号AD630J的Datasheet PDF文件第1页浏览型号AD630J的Datasheet PDF文件第2页浏览型号AD630J的Datasheet PDF文件第3页浏览型号AD630J的Datasheet PDF文件第5页浏览型号AD630J的Datasheet PDF文件第6页浏览型号AD630J的Datasheet PDF文件第7页 
AD630  
–Typical Performance Characteristics  
50mV  
1mV  
20mV  
10V  
5␮s  
1mV  
100  
90  
100  
90  
100  
90  
50mV/DIV  
؎10V 20kHz  
(V )  
i
(V )  
i
20mV/DIV  
(V )  
o
1mV/DIV  
(A)  
1mV/DIV  
(B)  
20mV/DIV  
10V/DIV  
10  
10  
10  
(V )  
0%  
(V )  
i
0%  
0%  
o
100mV/DIV  
500ns  
100mV  
(V )  
500ns  
20mV  
10V  
TOP TRACE: V  
MIDDLE TRACE: SETTLING  
ERROR (B)  
BOTTOM TRACE: V  
o
TOP TRACE: V  
TOP TRACE: V  
BOTTOM TRACE: V  
i
o
i
MIDDLE TRACE: SETTLING  
ERROR (A)  
BOTTOM TRACE: V  
i
15  
16  
o
o
5k⍀  
10k⍀  
2
10k⍀  
CH  
A
10k⍀  
20  
19  
18  
V
O
13  
12  
10k⍀  
1k⍀  
V
i
TOP  
TRACE  
15  
20  
2
14  
14  
10k⍀  
15  
20  
2
V
O
V
O
13  
13  
V
i
TOP  
TRACE  
CH  
B
CH A  
12  
BOTTOM  
TRACE  
CH A  
12  
BOTTOM  
TRACE  
10k⍀  
10k⍀  
10k⍀  
10k⍀  
MIDDLE  
TRACE  
(A)  
10k⍀  
(B)  
MIDDLE  
TRACE  
14  
9
V
i
30pF  
HP5082-2811  
TEKTRONIX  
7A13  
10  
Figure 9. Large Signal Inverting  
Step Response  
Figure 7. Channel-to-Channel Switch-  
Settling Characteristic  
Figure 8. Small Signal Noninverting  
Step Response  
TWO WAYS TO LOOK AT THE AD630  
R
5k⍀  
The functional block diagram of the AD630 (see page 1) also  
shows the pin connections of the internal functions. An alternative  
architectural diagram is shown in Figure 10. In this diagram, the  
individual A and B channel preamps, the switch, and the inte-  
grator output amplifier are combined in a single op amp. This  
amplifier has two differential input channels, only one of which  
is active at a time.  
A
16  
15  
V
i
R
10k⍀  
F
2
A
B
20  
V
O
19  
18  
13  
R
B
10k⍀  
+V  
S
14  
9
11  
15  
14  
16  
1
10  
R
5k⍀  
R
B
10k⍀  
A
Figure 11. AD630 Symmetric Gain ( 2)  
2.5k⍀  
R
2
F
A
B
10k⍀  
20  
19  
18  
When channel B is selected, the resistors RA and RF are con-  
nected for inverting feedback as shown in the inverting gain  
configuration diagram in Figure 12. The amplifier has sufficient  
loop gain to minimize the loading effect of RB at the virtual  
ground produced by the feedback connection. When the sign of  
the comparator input is reversed, input B will be deselected and  
A will be selected. The new equivalent circuit will be the nonin-  
verting gain configuration shown below. In this case RA will appear  
across the op-amp input terminals, but since the amplifier drives  
this difference voltage to zero the closed loop gain is unaffected.  
13  
12  
7
2.5k⍀  
17  
B/A  
9
SEL B  
SEL A  
10  
8
–V  
S
Figure 10. Architectural Block Diagram  
HOW THE AD630 WORKS  
The two closed loop gain magnitudes will be equal when RF/RA  
= 1 + RF/RB, which will result from making RA equal to RFRB/  
(RF + RB) the parallel equivalent resistance of RF and RB.  
The basic mode of operation of the AD630 may be more easy to  
recognize as two fixed gain stages which may be inserted into the  
signal path under the control of a sensitive voltage comparator.  
When the circuit is switched between inverting and noninverting  
gain, it provides the basic modulation/demodulation function. The  
AD630 is unique in that it includes Laser-Wafer-Trimmed thin-  
film feedback resistors on the monolithic chip. The configuration  
shown in Figure 11 yields a gain of 2 and can be easily changed to  
1 by shifting RB from its ground connection to the output.  
The 5k and the two 10k resistors on the AD630 chip can be  
used to make a gain of two as shown here. By paralleling the  
10k resistors to make RF equal 5k and omitting RB the circuit  
can be programmed for a gain of 1 (as shown in Figure 18a).  
These and other configurations using the on chip resistors  
present the inverting inputs with a 2.5k source impedance. The  
more complete AD630 diagrams show 2.5k resistors available at  
the noninverting inputs which can be conveniently used to mini-  
mize errors resulting from input bias currents.  
The comparator selects one of the two input stages to complete  
an operational feedback connection around the AD630. The  
deselected input is off and has negligible effect on the operation.  
–4–  
REV. C  
12345678

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