AD585JP

更新时间： 2024-02-06 05:02:50

品牌	Logo	应用领域
亚德诺 - ADI		采样保持电路放大器放大器电路
页数	文件大小	规格书
6页	342K
描述
High Speed, Precision Sample-and-Hold Amplifier

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技术参数
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AD585JP 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QLCC
包装说明：	QCCN, LCC20,.35SQ	针数：	20
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	7.7
Is Samacsys：	N	最长采集时间：	5 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	18 V
最小模拟输入电压：	-18 V	最大下降率：	1 V/s
JESD-30 代码：	S-CQCC-N20	JESD-609代码：	e4
长度：	8.89 mm	负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装等效代码：	LCC20,.35SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	+-12/+-15 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	2.54 mm	子类别：	Sample and Hold Circuit
最大压摆率：	10 mA	供电电压上限：	18 V
标称供电电压 (Vsup)：	15 V	表面贴装：	YES
温度等级：	MILITARY	端子面层：	Gold (Au)
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	8.89 mm	Base Number Matches：	1

AD585JP 数据手册

AD585

LOGIC INPUT

ence between the voltage being measured and the voltage previ-

ously measured determines the fraction by which the

dielectric absorption figure is multiplied. It is impossible to

readily correct for this error source. The only solution is to use a

capacitor with dielectric absorption less than the maximum

tolerable error. Capacitor types such as polystyrene, polypropy-

lene or Teflon are recommended.

The sample-and-hold logic control was designed for versatile

logic interfacing. The HOLD and HOLD inputs may be used

with both low and high level CMOS, TTL and ECL logic sys-

tems. Logic threshold programmability was achieved by using a

differential amplifier as the input stage for the digital inputs. A

predictable logic threshold may be programmed by referencing

either HOLD or HOLD to the appropriate threshold voltage.

For example, if the internal 1.4 V reference is applied to HOLD

an input signal to HOLD between +1.8 V and +V_Swill place

the AD585 in the hold mode. The AD585 will go into the

sample mode for this case when the input is between –V_Sand

+1.0 V. The range of references which may be applied is from

(–V_S+4 V) to (+V_S–3 V).

GROUNDING

Many data-acquisition components have two or more ground

pins which are not connected together within the device. These

“grounds” are usually referred to as the Logic Power Return

Analog Common (Analog Power Return), and Analog Signal

Ground. These grounds must be tied together at one point,

usually at the system power-supply ground. Ideally, a single

solid ground would be desirable. However, since current flows

through the ground wires and etch stripes of the circuit cards,

and since these paths have resistance and inductance, hundreds

of millivolts can be generated between the system ground point

and the ground pin of the AD585. Separate ground returns

should be provided to minimize the current flow in the path

from sensitive points to the system ground point. In this way

supply currents and logic-gate return currents are not summed

into the same return path as analog signals where they would

cause measurement errors.

OPTIONAL CAPACITOR SELECTION

If an additional capacitor is going to be used in conjunction

with the internal 100 pF capacitor it must have a low dielectric

absorption. Dielectric absorption is just that; it is the charge

absorbed into the dielectric that is not immediately added to or

removed from the capacitor when rapidly charged or discharged.

The capacitor with dielectric absorption is modeled in Figure 14.

Figure 14. Capacitor Model with Dielectric Absorption

If the capacitor is charged slowly, C_DAwill eventually charge to

the same value as C. But unfortunately, good dielectrics have

very high resistances, so while C_DAmay be small, R_Xis large and

the time constant R_XC_DAtypically runs into the millisecond

range. In fast charge, fast-discharge situations the effect of di-

electric absorption resembles “memory”. In a data acquisition

system where many channels with widely varying data are being

sampled the effect is to have an ever changing offset which ap-

pears as a very nonlinear sample-to-hold offset since the differ-

Figure 15. Basic Grounding Practice

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Terminal PLCC (P-20A)

20-Terminal LCC (E-20A)

14-Pin Cerdip (Q-14)

–6–

REV. A

1...3 4 56

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