AD585JP

更新时间： 2024-02-19 06:54:09

品牌	Logo	应用领域
亚德诺 - ADI		采样保持电路放大器放大器电路
页数	文件大小	规格书
6页	342K
描述
High Speed, Precision Sample-and-Hold Amplifier

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技术参数
数据手册

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AD585JP 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QLCC
包装说明：	QCCN, LCC20,.35SQ	针数：	20
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	7.7
Is Samacsys：	N	最长采集时间：	5 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	18 V
最小模拟输入电压：	-18 V	最大下降率：	1 V/s
JESD-30 代码：	S-CQCC-N20	JESD-609代码：	e4
长度：	8.89 mm	负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装等效代码：	LCC20,.35SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	+-12/+-15 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	2.54 mm	子类别：	Sample and Hold Circuit
最大压摆率：	10 mA	供电电压上限：	18 V
标称供电电压 (Vsup)：	15 V	表面贴装：	YES
温度等级：	MILITARY	端子面层：	Gold (Au)
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	8.89 mm	Base Number Matches：	1

AD585JP 数据手册

AD585

For the AD585 in particular it becomes:

0.3 pC

100 pF + C

HOLD-TO-SAMPLE TRANSITION

The Nyquist theorem states that a band-limited signal which is

sampled at a rate at least twice the maximum signal frequency

can be reconstructed without loss of information. This means

that a sampled data system must sample, convert and acquire

the next point at a rate at least twice the signal frequency. Thus

the maximum input frequency is equal to

S/H Offset (V ) =

(

)

EXT

The addition of an external hold capacitor also affects the acqui-

sition time of the AD585. The change in acquisition time with

respect to the C_EXTis shown graphically in Figure 2.

f_MAX

HOLD MODE

2 T

(

+T_CONV+T_AP

)

ACQ

In the hold mode there are two important specifications that

must be considered; feedthrough and the droop rate. Feedthrough

errors appear as an attenuated version of the input at the output

while in the hold mode. Hold-Mode feedthrough varies with fre-

quency, increasing at higher frequencies. Feedthrough is an im-

portant specification when a sample and hold follows an analog

multiplexer that switches among many different channels.

Where T_ACQis the acquisition time of the sample-to-hold

amplifier, T_APis the maximum aperture time (small enough to

be ignored) and T_CONVis the conversion time of the A/D

converter.

DATA ACQUISITION SYSTEMS

The fast acquisition time of the AD585 when used with a high

speed A/D converter allows accurate digitization of high fre-

quency signals and high throughput rates in multichannel data

acquisition systems. The AD585 can be used with a number of

different A/D converters to achieve high throughput rates. Fig-

ures 12 and 13 show the use of an AD585 with the AD578 and

AD574A.

Hold-mode droop rate is the change in output voltage per unit

of time while in the hold mode. Hold-mode droop originates as

leakage from the hold capacitor, of which the major leakage

current contributors are switch leakage current and bias current.

The rate of voltage change on the capacitor dV/dT is the ratio of

the total leakage current I_Lto the hold capacitance C_H.

dV_OUT

I_L(pA)

Droop Rate =

(Volts/Sec) =

_H(pF)

For the AD585 in particular;

100 pA

100 pF +(C_EXT

Droop Rate =

)

Additionally the leakage current doubles for every 10°C increase

in temperature above 25°C; therefore, the hold-mode droop rate

characteristic will also double in the same fashion. The hold-mode

droop rate can be traded-off with acquisition time to provide the

best combination of droop error and acquisition time. The tradeoff

is easily accomplished by varying the value of C_EXT

Since a sample and hold is used typically in combination with

an A/D converter, then the total droop in the output voltage has

to be less than 1/2 LSB during the period of a conversion. The

maximum allowable signal change on the input of an A/D

converter is:

Figure 12. A/D Conversion System, 117.6 kHz Throughput

58.8 kHz max Signal Input

Full -Scale Voltage

∆V max =

2⁽^{N +1}

)

Once the maximum ∆V is determined then the conversion time

of the A/D converter (T_CONV) is required to calculate the maxi-

mum allowable dV/dT.

∆V max

T_CONV

max =

dV max

The maximum

as shown by the previous equation is

the limit not only at 25°C but at the maximum expected operat-

ing temperature range. Therefore, over the operating temperature

range the following criteria must be met (T_OPERATION–25°C)

Figure 13. 12-Bit A/D Conversion System, 26.3 kHz

Throughput Rate, 13.1 kHz max Signal Input

= ∆T.

∆T °C

(

)

dV 25°C

dV max

10°C

× 2

≤

REV. A

–5–

1 2 3 456

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