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AD5744CSUZ-REEL7 PDF预览

AD5744CSUZ-REEL7

更新时间: 2024-01-31 10:59:50
品牌 Logo 应用领域
亚德诺 - ADI 输入元件转换器
页数 文件大小 规格书
32页 463K
描述
IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32, LEAD FREE, PLASTIC, MS-026ABA, TQFP-32, Digital to Analog Converter

AD5744CSUZ-REEL7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:MS-026ABA, TQFP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
最大模拟输出电压:10.5263 V最小模拟输出电压:-10.5263 V
转换器类型:D/A CONVERTER输入位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输入格式:SERIALJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
最大线性误差 (EL):0.0061%湿度敏感等级:1
标称负供电电压:-15 V位数:14
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装等效代码:TQFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):225
电源:3/5,+-12/+-15 V认证状态:Not Qualified
座面最大高度:1.2 mm最大稳定时间:10 µs
标称安定时间 (tstl):8 µs子类别:Other Converters
最大压摆率:14 mA标称供电电压:15 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

AD5744CSUZ-REEL7 数据手册

 浏览型号AD5744CSUZ-REEL7的Datasheet PDF文件第4页浏览型号AD5744CSUZ-REEL7的Datasheet PDF文件第5页浏览型号AD5744CSUZ-REEL7的Datasheet PDF文件第6页浏览型号AD5744CSUZ-REEL7的Datasheet PDF文件第8页浏览型号AD5744CSUZ-REEL7的Datasheet PDF文件第9页浏览型号AD5744CSUZ-REEL7的Datasheet PDF文件第10页 
Preliminary Technical Data  
TIMING CHARACTERISTICS  
AD5744  
AVDD = 11ꢀ4 V to 1ꢁꢀ5 V, AVꢃꢃ = −11ꢀ4 V to −1ꢁꢀ5 V, AGND = DGND = REFGND = PGND = ꢂ V; REFAB = REFCD = 5 V;  
DVCC = 2ꢀ7 V to 5ꢀ25 V, RLOAD = 1ꢂ kΩ, CL = 2ꢂꢂ pFAll specifications TMIN to TMAX, unless otherwise notedꢀ  
Table 4.  
Parameter1, 2, 3  
ꢀimit at TMIN, TMAX  
Unit  
Description  
t1  
t2  
t3  
t4  
33  
13  
13  
13  
13  
40  
2
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
μs min  
ns min  
ns min  
ns max  
μs max  
ns min  
μs max  
ns max  
ns min  
μs min  
ns min  
SCLK cycle time  
SCLK high time  
SCLK low time  
SYNC falling edge to SCLK falling edge setup time  
24th SCLK falling edge to SYNC rising edge  
Minimum SYNC high time  
Data setup time  
4
t5  
t6  
t7  
t8  
t9  
5
Data hold time  
1.4  
400  
10  
500  
10  
10  
2
SYNC rising edge to LDAC falling edge (all DACs updated)  
SYNC rising edge to LDAC falling edge (single DAC updated)  
LDAC pulse width low  
t10  
t11  
t12  
t13  
t14  
LDAC falling edge to DAC output response time  
DAC output settling time  
CLR pulse width low  
CLR pulse activation time  
5, 6  
t15  
25  
20  
2
SCLK rising edge to SDO valid  
t16  
t17  
t18  
SYNC rising edge to SCLK rising edge  
SYNC rising edge to DAC output response time (LDAC = 0)  
LDAC falling edge to SYNC rising edge  
170  
1 Guaranteed by design and characterization; not production tested.  
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.  
3 See Figure 2, Figure 3, and Figure 4.  
4 Standalone mode only.  
5 Measured with the load circuit of Figure 5.  
6 Daisy-chain mode only.  
Rev. PrE | Page 7 of 32  
 

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