AD573KD

更新时间： 2024-01-27 01:54:51

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	330K
描述
10-Bit A/D Converter

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD573KD 技术参数

Source Url Status Check Date：	2013-05-01 14:56:14.576	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	DIP	包装说明：	DIP, DIP20,.3
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	7.77	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最长转换时间：	30 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	R-CDIP-T20
JESD-609代码：	e0	长度：	25.4 mm
最大线性误差 (EL)：	0.0977%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	10
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-12/-15 V	认证状态：	Not Qualified
采样速率：	0.05 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	5.08 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	NO
技术：	BIPOLAR	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

AD573KD 数据手册

AD573

CONVERT Pulse Generation

This mode is particularly useful for bench-testing of the AD573,

and in applications where dedicated I/O ports of peripheral in-

terface adapter chips are available.

The AD573 is tested with a CONVERT pulse width of 500 ns

and will typically operate with a pulse as short as 300 ns.

However, some microprocessors produce active WR pulses

which are shorter than this. Either of the circuits shown in Fig-

ure 13 can be used to generate an adequate CONVERT pulse

for the AD573.

In both circuits, the short low going WR pulse sets the

CONVERT line high through a flip-flop. The rising edge of

DR (which signifies that the internal logic has been reset) resets

the flip-flop and brings CONVERT low, which starts the

conversion.

Figure 15. AD573 in “Stand-Alone“ Mode

(Output Data Valid 500 ns After DR Goes Low)

Note that t_DSCis slightly longer when the result of the previous

conversion contains a Logic 1 on the LSB. This means that the

actual CONVERT pulse generated by the circuits in Figure 13

will vary slightly in width.

Apple II Microcomputer Interface

The AD573 can provide a flexible, low cost analog interface for

the popular Apple II microcomputer. The Apple II, based on a

1 MHz 6502 microprocessor, meets all timing requirements for

the AD573. Only a few TTL gates are required to decode the

signals available on the Apple II’s peripheral connector. The

recommended connections are shown in Figure 16.

Figure 13a. Using 74LS00

Figure 13b. Using 1/2 74LS74

Output Data Format

The AD573 output data is presented in a left justified format.

The 8 MSBs (DB9–DB2, Pins 10 through 3) are enabled by

HBE (Pin 20) and the 2 LSBs (DB1, DB0—Pins 2 and 1) are

enabled by LBE (Pin 19). This allows simple interface to 8-bit

system buses by overlapping the 2 MSBs and the 2 LSBs. The

organization of the data is shown in Figure 14.

When the least significant bits are read (LBE brought low), the

six remaining bits of the byte will contain meaningless data.

These unwanted bits can be masked by logically ANDing the

byte with 11000000 (C0 hex), which forces the 6 lower bits to

Logic 0 while preserving the two most significant bits of the byte.

Note that it is not possible to reconfigure the AD573 for right

justified data.

Figure 16. AD573 Interface to Apple ll

The BASIC routine listed here will operate the AD573 circuit

shown in Figure 16. The conversion is started by POKEing to

the location which contains the AD573. The relatively slow ex-

ecution speed of BASIC eliminates the need for a delay routine

between starting and reading the converter. This routine as-

sumes that the AD573 is connected for a ±5 volt input range.

Variable I represents the integer value (from 0 to 1023) read

from the AD573. Variable V represents the actual value of the

input signal (in volts).

Figure 14. AD573 Output Data Format

In systems where all 10 bits are desired at the same time, HBE

and LBE may be tied together. This is useful in interfacing to

16-bit bus systems. The resulting 10-bit word can then be

placed at the high end of the 16-bit bus for left justification or at

the low end for right justification.

It is also possible to use the AD573 in a “stand-alone” mode,

where the output data buffers are automatically enabled at the

end of a conversion cycle. In this mode, the DR output is wired

to the HBE and LBE inputs. The outputs thus are forced into

the high impedance state during the conversion period, and

valid data becomes available approximately 500 ns after the DR

signal goes low at the end of the conversion. The 500 ns delay

allows propagation of the least significant bit through the inter-

nal logic.

100 PRINT “WHICH SLOT IS THE A/D IN”;:INPUT S

110 A=49280 + 16*S

120 POKE A,0

130 L=PEEK(A) :H=PEEK(A+1)

140 I =(4*H) + INT(L/64)

150 V=(I/1024)*10-5

160 PRINT “THE INPUT SIGNAL IS”;V;“VOLTS.”

REV. A

–7–

1...4 5 678

下载PDF

与AD573KD相关器件

型号	品牌	描述	获取价格	数据表
AD573KD/+	ADI	IC IC,A/D CONVERTER,SINGLE,10-BIT,BIPOLAR,DIP,20PIN, Analog to Digital Converter	获取价格
AD573KN	ADI	10-Bit A/D Converter	获取价格
AD573KN/+	ADI	IC IC,A/D CONVERTER,SINGLE,10-BIT,BIPOLAR,DIP,20PIN, Analog to Digital Converter	获取价格
AD573KNZ	ADI	10-Bit A/D Converter	获取价格
AD573KP	ADI	10-Bit A/D Converter	获取价格
AD573SD	ADI	10-Bit A/D Converter	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AD573KD

AD573KD 技术参数

AD573KD 数据手册

与AD573KD相关器件

与AD573KD相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD573KD

AD573KD 技术参数

AD573KD 数据手册

与AD573KD相关器件

与AD573KD相关文章

您还可以找

您在本页遇到什么问题？