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AD570SCHIPS

更新时间： 2024-01-07 05:41:36

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	310K
描述
IC 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC18, DIE-16, Analog to Digital Converter

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AD570SCHIPS 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIE
包装说明：	DIE, DIE OR CHIP	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.72
最大模拟输入电压：	5 V	最小模拟输入电压：	-5 V
最长转换时间：	40 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-XUUC-N18	最大线性误差 (EL)：	0.2%
标称负供电电压：	-15 V	模拟输入通道数量：	1
位数：	8	功能数量：	1
端子数量：	18	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	BINARY, OFFSET BINARY
输出格式：	PARALLEL, 8 BITS	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	RECTANGULAR	封装形式：	UNCASED CHIP
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5,-12/-15 V
认证状态：	Not Qualified	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	MILITARY
端子形式：	NO LEAD	端子位置：	UPPER
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

AD570SCHIPS 数据手册

AD570

INTERFACING THE AD570 TO A MICROPROCESSOR

The AD570 can easily be arranged to be driven from standard

microprocessor control lines and to present data to any standard

microprocessor bus (4-, 8-, 12- or 16-bit) with a minimum of

additional control components. The configuration shown in

Figure 13 is designed to operate with an 8-bit bus and standard

8080 control signals.

BUS INTERFACING WITH A PERIPHERAL INTERFACE

CIRCUIT

An improved technique for interfacing to a µP bus involves the

use of special peripheral interfacing circuits (or I/O devices),

such as the MC6821 Peripheral Interface Adapter (PIA). Shown

in Figure 14 is a straightforward application of a PIA to multi-

plex up to 10 AD570 circuits. The AD570 has 3-state outputs,

hence the data bit outputs can be paralleled, provided that only

one converter at a time is permitted to be the active state. The

DATA READY output of the AD570 is an open collector with

resistor pull-up, thus several DR lines can be wire-ORed to

allow indication of the status of the selected device. One of the

8-bit ports of the PIA is programmed as an 8-bit input port. The

8-bits of the second port are programmed as outputs, and along

with the 2 control bits (which act as outputs), are used to con-

trol the 10 AD570s. When a control line is in the “1” or high

state, the ADC will be automatically blanked. That is, its out-

puts will be in the inactive open state. If a single control line is

switched low, its ADC will convert and the outputs will auto-

matically go active when the conversion is complete. The result

can then be read from port A. When the next conversion is

desired, a different control line can be switched to zero, blank-

ing the previously active port at the same time. Subsequently,

this second device can be read by the microprocessor, and so-

forth. The status lines are wire-ORed in 2 groups and connected

to the two remaining control pins. This allows a conversion sta-

tus check to be made after a convert command, if necessary.

The ADCs are divided into two groups to minimize the loading

effect of the internal pull-up resistors on the DATA READY

buffers. See the MC6821 data sheet for more application detail.

The input control circuitry shown is required to ensure that the

AD570 receives a sufficiently long B & C input pulse. When the

converter is ready to start a new conversion, the B & C line is

low, and DR is low. To command a conversion, the start ad-

dress decode line goes low, followed by WR. The B & C line

will now go high, followed about 1.5 µs later by DR. This resets

the external flip-flop and brings B & C back to low, which ini-

tiates the conversion cycle. At the end of the conversion cycle,

the DR line goes low, the data outputs will become active with

the new data and the control lines will return to the standby

state. The new data will remain active until a new conversion is

commanded. The self-pulsing nature of this circuit guarantees a

sufficient convert pulse width.

This new data can now be presented to the data bus by en-

abling the three-state buffers when desired. An 8-bit data

word is loaded onto the bus when its decoded address goes

low and the RD line goes low. Polling the converter to deter-

mine if conversion is complete can be done by addressing the

Figure 13. Interfacing AD570 to an 8-Bit Bus

(8080 Control Structure)

gate (shown dotted) which buffers the DR line, if desired. In

this configuration, there is no need for additional buffer register

storage. The data is stored indefinitely in the, since the B & C

line is continually held low.

Figure 14. Multiplexing 10 AD570s Using Single PIA for

µP Interface. No Other Logic Required (6800 Control

Structure)

REV. A

–7–

1...4 5 678

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AD570SD/883B	ETC	Analog-to-Digital Converter， 8-Bit	获取价格
AD571	ADI	10-Bit A/D Converter	获取价格
AD571*	ETC	10-Bit A/D Converter	获取价格
AD571J	ADI	10-Bit A/D Converter	获取价格
AD571JCHIPS	ADI	暂无描述	获取价格

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