Datasheet > AD570SCHIPS

AD570SCHIPS

更新时间： 2024-02-23 14:40:33

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	310K
描述
IC 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC18, DIE-16, Analog to Digital Converter

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AD570SCHIPS 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIE
包装说明：	DIE, DIE OR CHIP	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.72
最大模拟输入电压：	5 V	最小模拟输入电压：	-5 V
最长转换时间：	40 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-XUUC-N18	最大线性误差 (EL)：	0.2%
标称负供电电压：	-15 V	模拟输入通道数量：	1
位数：	8	功能数量：	1
端子数量：	18	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	BINARY, OFFSET BINARY
输出格式：	PARALLEL, 8 BITS	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	RECTANGULAR	封装形式：	UNCASED CHIP
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5,-12/-15 V
认证状态：	Not Qualified	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	MILITARY
端子形式：	NO LEAD	端子位置：	UPPER
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

AD570SCHIPS 数据手册

AD570

the DR and data lines will not change. If a 2 µs or longer pulse

is applied to the B & C line during a conversion, the converter

will clear and start a new conversion cycle.

Figure 11. Multiplex Mode

SAMPLE-HOLD AMPLIFIER CONNECTION TO THE

AD570

Many situations in high-speed acquisition systems or digitizing

of rapidly changing signals require a sample-hold amplifier

(SHA) in front of the A-D converter. The SHA can acquire and

hold a signal faster than the converter can perform a conversion.

A SHA can also be used to accurately define the exact point in

time at which the signal is sampled. For the AD570, a SHA can

also serve as a high input impedance buffer.

Figure 9. AD570 Timing and Control Sequence

CONTROL MODES WITH BLANK AND CONVERT

Figure 12 shows the AD570 connected to the AD582 mono-

lithic SHA for high speed signal acquisition. In this configura-

tion, the AD582 will acquire a 10 volt signal in less than 10 µs

with a droop rate less than 100 µV/ms. The control signals are

arranged so that when the control line goes low, the AD582 is put

into the “hold” mode, and the AD570 will begin its conversion

cycle. (The AD582 settles to final value well in advance of the

The timing sequence of the AD570 discussed above allows the

device to be easily operated in a variety of systems with differing

control modes. The two most common control modes, the Con-

vert Pulse Mode, and the Multiplex Mode, are illustrated here.

Convert Pulse Mode–In this mode, data is present at the output

of the converter at all times except when conversion is taking

place. Figure 10 illustrates the timing of this mode. The BLANK

and CONVERT line is normally low and conversions are trig-

gered by a positive pulse. A typical application for this timing

mode is shown in Figure 13, in which µP bus interfacing is

easily accomplished with three-state buffers.

Multiplex Mode—In this mode the outputs are blanked except

when the device is selected for conversion and readout; this tim-

ing is shown in Figure 11. A typical AD570 multiplexing appli-

cation is shown in Figure 14.

This operating mode allows multiple AD570 devices to drive

common data lines. All BLANK and CONVERT lines are held

high to keep the outputs blanked. A single AD570 is selected, its

BLANK and CONVERT line is driven low and at the end of

conversion, which is indicated by DATA READY going low, the

conversion result will be present at the outputs. When this data

has been read from the 8-bit bus, BLANK and CONVERT is

restored to the blank mode to clear the data bus for other con-

verters. When several AD570s are multiplexed in sequence, a

new conversion may be started in one AD570 while data is

being read from another. As long as the data is read and the first

AD570 is cleared within 15 µs after the start of conversion of the

second AD570, no data overlap will occur.

Figure 12. Sample-Hold Interface to the AD570

first comparator decision inside the AD570). The DATA

READY line is fed back to the other side of the differential

input control gate so that the AD582 cannot come out of the

“hold” mode during the conversion cycle. At the end of the con-

version cycle, the DATA READY line goes low, automatically

placing the AD582 back into the sample mode. This feature al-

lows simple control of both the SHA and the A-D converter

with a single line. Observe carefully the ground, supply, and by-

pass capacitor connections between the two devices. The ar-

rangement minimizes ground noise and interference during the

conversion cycle to give the most accurate measurements.

Figure 10. Convert Pulse Mode

–6–

REV. A

1...3 4 567 8

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