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AD538ADZ PDF预览

AD538ADZ

更新时间： 2024-02-19 01:52:47
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER /
页数 文件大小 规格书
13页 929K
描述
ANALOG MULTIPLE FUNCTIONS, 0.4 MHz BAND WIDTH, CDIP18, ROHS COMPLIANT, SIDE BRAZED, CERAMIC, DIP-18

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AD538ADZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：ROHS COMPLIANT, SIDE BRAZED, CERAMIC, DIP-18针数：18
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.57
模拟集成电路 - 其他类型：ANALOG MULTIPLE FUNCTIONS标称带宽：0.4 MHz
JESD-30 代码：R-CDIP-T18JESD-609代码：e4
长度：22.865 mm负电源电压最大值（Vsup）：-18 V
负电源电压最小值（Vsup）：-4.5 V标称负供电电压 (Vsup)：-15 V
最大负输入电压：功能数量：1
端子数量：18最高工作温度：85 °C
最低工作温度：-25 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP18,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED最大正输入电压：10 V
电源：+-15 V认证状态：Not Qualified
座面最大高度：4.32 mm子类别：Analog Computational Functions
最大供电电流 (Isup)：7 mA最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：15 V
表面贴装：NO技术：BIPOLAR
温度等级：OTHER端子面层：Gold (Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

AD538ADZ 数据手册

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AD538  
150  
100  
10  
FOR THE FREQUENCY RANGE OF 10Hz  
TO 100kHz THE TOTAL RMS OUTPUT  
100  
NOISE, e , FOR A GIVEN BANDWIDTH  
o
Bw, IS CALCULATED e = e Bw  
o
n
V
V
V
= 10V  
X
Y
Z
V
= 0.01V  
10  
X
= 5V +5V SIN ␻t VOLTS  
= 0V  
1
1.0  
0.1  
V
= 10V  
X
0.10  
0.01  
0.01  
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
DC OUTPUT VOLTAGE – Volts  
INPUT FREQUENCY – Hz  
Figure 7. VY Feedthrough vs. Frequency  
Figure 8. 1 kHz Output Noise Spectral Density vs. DC Output  
Voltage  
Under normal operation, the log-ratio output will be directly  
connected to a second functional block at input C, the antilog  
subsection. This section performs the antilog according to the  
transfer function:  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
I
A
D
Z
LOG  
25k⍀  
RATIO  
V
Z
B
+10V  
+2V  
I
X
⎛
⎞
q
kT  
VO = VY e ⎜⎝VC  
⎟
⎠
V
X
25k⍀  
100⍀  
100⍀  
As with the log-ratio circuit included in the AD538, the user  
may use the antilog subsection by itself. When both subsections  
are combined, the output at B is tied to C, the transfer function  
of the AD538 computational unit is:  
SIGNAL  
GND  
INTERNAL  
VOLTAGE  
PWR  
GND  
+V  
S
S
REFERENCE  
AD538  
–V  
C
OUTPUT  
⎡
⎤
⎥
⎛
⎞ ⎛  
⎞
⎛
⎞
kT  
q
q
kT  
VZ  
V
X
ln  
VO = VY e ⎢⎣⎢⎜⎝  
⎥⎦ ;VB = VC  
⎟ ⎜  
⎠ ⎝  
⎟
⎠
⎜
⎝
⎟
⎠
25k⍀  
V
I
Y
O
ANTILOG  
which reduces to:  
I
V
LOG  
Y
25k⍀  
⎛
⎜
⎞
V
Z
V
O
= V  
Y
⎟
V
X
Figure 9. Functional Block Diagram  
⎝
⎠
Finally, by increasing the gain, or attenuating the output of the  
log ratio subsection via resistor programming, it is possible to  
raise the quantity VZ/VX to the mth power. Without external  
programming, m is unity. Thus the overall AD538 transfer  
function equals:  
FUNCTIONAL DESCRIPTION  
As shown in Figures 9 and 10, the VZ and VX inputs connect  
directly to the AD538’s input log ratio amplifiers. This subsec-  
tion provides an output voltage proportional to the natural log  
of input voltage VZ, minus the natural log of input voltage VX.  
The output of the log ratio subsection at B can be expressed by  
the transfer function:  
m
⎛
⎞
VZ  
VO = VY  
⎜
⎟
V
⎝
⎠
X
⎛
⎞
kT  
q
VZ  
V
VB  
=
ln  
⎜
⎟
where 0.2 < m < 5.  
⎝
⎠
X
When the AD538 is used as an analog divider, the VY input can  
be used to multiply the ratio VZ /VX by a convenient scale factor.  
The actual multiplication by the VY input signal is accomplished  
by adding the log of the VY input signal to the signal at C, which  
is already in the log domain.  
where k = 1.3806 × 10–23 J/K,  
q = 1.60219 × 10–19 C,  
T is in Kelvins.  
The log ratio configuration may be used alone, if correctly tem-  
perature compensated and scaled to the desired output level  
(see Applications section).  
REV. D  
–6–  
1...45678910...13

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