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AD5363BSTZ PDF预览

AD5363BSTZ

更新时间: 2024-01-07 04:27:15
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 输入元件
页数 文件大小 规格书
29页 1719K
描述
SERIAL INPUT LOADING, 20us SETTLING TIME, 14-BIT DAC, PQFP52, ROHS COMPLIANT, MS-026BCC, LQFP-52

AD5363BSTZ 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:52
Reach Compliance Code:unknown风险等级:5.77
Is Samacsys:N最大模拟输出电压:15.1 V
最小模拟输出电压:-15.1 V转换器类型:D/A CONVERTER
输入位码:2'S COMPLEMENT BINARY输入格式:SERIAL
JESD-30 代码:S-PQFP-G52JESD-609代码:e3
长度:10 mm最大线性误差 (EL):0.0061%
湿度敏感等级:3标称负供电电压:-15 V
位数:14功能数量:1
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:1.6 mm
标称安定时间 (tstl):20 µs标称供电电压:15 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

AD5363BSTZ 数据手册

 浏览型号AD5363BSTZ的Datasheet PDF文件第1页浏览型号AD5363BSTZ的Datasheet PDF文件第2页浏览型号AD5363BSTZ的Datasheet PDF文件第3页浏览型号AD5363BSTZ的Datasheet PDF文件第5页浏览型号AD5363BSTZ的Datasheet PDF文件第6页浏览型号AD5363BSTZ的Datasheet PDF文件第7页 
AD5362/AD5363  
GENERAL DESCRIPTION  
The AD5362/AD5363 contain eight 16-/14-bit DACs in a single  
52-lead LQFP package or 56-lead LFCSP package. The devices  
provide buffered voltage outputs with a span of 4× the reference  
voltage. The gain and offset of each DAC can be independently  
trimmed to remove errors. For even greater flexibility, the device  
is divided into two groups of four DACs, and the output range  
of each group can be independently adjusted by an offset DAC.  
The AD5362/AD5363 have a high speed 4-wire serial interface  
that is compatible with SPI, QSPI™, MICROWIRE™, and DSP  
interface standards and can handle clock speeds of up to  
50 MHz. All the outputs can be updated simultaneously by  
LDAC  
taking the  
input low. Each channel has a programmable  
gain and an offset adjust register.  
Each DAC output is gained and buffered on chip with respect  
to an external SIGGNDx input. The DAC outputs can also be  
The AD5362/AD5363 offer guaranteed operation over a wide  
supply range with VSS from −16.5 V to −4.5 V and VDD from 8 V  
to 16.5 V. The output amplifier headroom requirement is 1.4 V,  
operating with a load current of 1 mA.  
CLR  
switched to SIGGNDx via the  
pin.  
Table 1. High Channel Count Bipolar DACs  
Model  
Resolution (Bits)  
Nominal Output Span  
4 × VREF (20 V)  
4 × VREF (20 V)  
4 × VREF (20 V)  
4 × VREF (20 V)  
4 × VREF (12 V)  
4 × VREF (12 V)  
4 × VREF (12 V)  
4 × VREF (12 V)  
8.75 V  
Output Channels  
Linearity Error (LSB)  
AD5360  
AD5361  
AD5362  
AD5363  
AD5370  
AD5371  
AD5372  
AD5373  
AD5378  
AD5379  
16  
14  
16  
14  
16  
14  
16  
14  
14  
14  
16  
16  
8
4
1
4
1
4
1
4
1
3
3
8
40  
40  
32  
32  
32  
40  
8.75 V  
Rev. A | Page 3 of 28  
 

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