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AD5348_15

更新时间： 2022-02-26 12:08:16

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亚德诺 - ADI		/
页数	文件大小	规格书
24页	476K
描述
2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs

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AD5348_15 数据手册

AD5346/AD5347/AD5348

TIMING CHARACTERISTICS^{1, 2, 3}

Table 3. V_DD= 2.5 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted

Parameter

Limit at T_MIN, T_MAX

Unit

Condition/Comments

Data Write Mode (Figure 3)

CS to WR setup time

CS to WR hold time

WR pulse width

Data, GAIN, BUF setup time

Data, GAIN, BUF hold time

Synchronous mode. WR falling to LDAC falling.

Synchronous mode. LDAC falling to WR rising.

t₁

t₂

t₃

t₄

t₅

t₆

t₇

4.5

ns min

rising to LDAC rising.

t₈

4.5

ns min

Synchronous mode.

Asynchronous mode. LDAC rising to WR rising.

Asynchronous mode. WR rising to LDAC falling.

LDAC pulse width

t₉

t₁₀

t₁₁

ns min

4.5

CLR

t₁₂

t₁₃

t₁₄

t₁₅

pulse width

Time between WR cycles

A0, A1, A2 setup time

A0, A1, A2 hold time

Data Readback Mode (Figure 4)

t₁₆

t₁₇

ns min

ns max

ns min

ns max

ns min

A0, A1, A2 to setup time

A0, A1, A2 to hold time

CS to falling edge of

t₁₈

t₁₉

RD pulse width; V_DD= 3.6 V to 5.5 V

RD pulse width; V_DD= 2.5 V to 3.6 V

CS to RD hold time

Data access time after falling edge of RD; V_DD= 3.6 V to 5.5 V

Data access time after falling edge of RD V_DD= 2.5 V to 3.6 V

Bus relinquish time after rising edge of RD

t₂₀

t₂₁

t₂₂

t₂₃

CS falling edge to data; V_DD= 3.6 V to 5.5 V

CS falling edge to data; V_DD= 2.5 V to 3.6 V

t₂₄

t₂₅

t₂₆

Time between

cycles

Time from RD to WR

Time from WR to RD, V_DD= 3.6 V to 5.5 V

Time from WR to RD, V_DD= 2.5 V to 3.6 V

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 2.

t₁

t₂

A0–A2

t₃

t₁₃

t₁₇

t₁₆

t₅

t₄

DATA,

GAIN, BUF

t₁₈

t₂₀

t₁₉

t₂₄

t₆

t₈

t₇

t₉

DATA

LDAC

t₂₁

t₂₂

t₁₀

t₁₁

LDAC

t₂₃

t₁₂

CLR

t₂₅

t₁₄

t₁₅

A0–A2

t₂₆

NOTES

1. SYNCHRONOUS LDAC UPDATE MODE

2. ASYNCHRONOUS LDAC UPDATE MODE

Figure 3. Parallel Interface Write Timing Diagram

Figure 4. Parallel Interface Read Timing Diagram

Rev. 0 | Page 5 of 24

1 2 3 456 7 8...24

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