Datasheet > AD5321BRTZ-REEL1

AD5321BRTZ-REEL1

更新时间： 2022-04-12 13:54:56

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	429K
描述
2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AD5321BRTZ-REEL1 数据手册

AD5301/AD5311/AD5321

AC CHARACTERISTICS¹

V_DD= 2.5 V to 5.5 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

B Version²

Parameter³

Min

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time

AD5301

AD5311

V_DD= 5 V

ꢀ

μs

1/4 scale to 3/4 scale change (0x40 to 0xC0)

1/4 scale to 3/4 scale change (0x100 to 0x300)

1/4 scale to 3/4 scale change (0x400 to 0xC00)

AD5321

Slew Rate

Major-Code Change Glitch Impulse

Digital Feedthrough

0.7

0.3

V/μs

nV-s

1 LSB change around major carry

¹See the Terminology section.

²Temperature range for the B Version is as follows: –40°C to +105°C.

³Guaranteed by design and characterization, not production tested.

TIMING CHARACTERISTICS¹

V_DD= 2.5 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Limit at T_MIN, T_MAX

Parameter²

(B Version)

Unit

Conditions/Comments

f_SCL

t₁

t₂

t₃

t₄

400

2.5

0.ꢀ

1.3

0.ꢀ

100

0.9

0.ꢀ

1.3

300

kHz max

μs min

ns min

μs max

μs min

ns max

ns min

ns max

ns min

pF max

SCL clock frequency

SCL cycle time

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD,STA, start/repeated start condition hold time

t_SU,DAT,data setup time

t_HD,DAT, data hold time

t₅

t_ꢀ

t₇

t₈

t₉

t₁₀

t_SU,STA, setup time for repeated start

t_SU,STO, stop condition setup time

t_BUF, bus free time between a stop condition and a start condition

t_R, rise time of both SCL and SDA when receiving⁴

May be CMOS driven

t_F, fall time of SDA when receiving⁴

t_F, fall time of both SCL and SDA when transmitting⁴

t₁₁

250

300

20 + 0.1C_b

C_b

400

Capacitive load for each bus line

¹See Figure 2.

²Guaranteed by design and characterization, not production tested.

³A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the V_{IH MIN}of the SCL signal) in order to bridge the undefined region of SCL’s

falling edge.

⁴t_Rand t_Fmeasured between 0.3 V_DDand 0.7 V_DD

⁵C_bis the total capacitance of one bus line in picofarads.

SDA

t₁₁

t₉

t₃

t₄

t₁₀

SCL

t₂

t₅

t₄

t₆

t₁

t₇

t₈

START

CONDITION

REPEATED

STOP

CONDITION

START

CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. B | Page 5 of 24

1 2 3 456 7 8...24

下载PDF

与AD5321BRTZ-REEL1相关器件

型号	品牌	描述	获取价格	数据表
AD5321BRTZ-REEL71	ADI	2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Vo	获取价格
AD5322	ADI	+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs	获取价格
AD5322ARM	ADI	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V	获取价格
AD5322ARM	ROCHESTER	SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO10, MO-187BA, MSOP-10	获取价格
AD5322ARM-REEL7	ADI	2.5 V to 5.5 V, 230 Î¼A, Dual Rail-to-Rail, V	获取价格
AD5322ARM-REEL7	ROCHESTER	SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO10, MO-187BA, MSOP-10	获取价格