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AD5320BRM PDF预览

AD5320BRM

更新时间: 2024-01-26 09:11:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
12页 193K
描述
+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 12-Bit DAC in a SOT-23

AD5320BRM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:LSSOP,针数:6
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:N最大模拟输出电压:5.5 V
最小模拟输出电压:转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:2.9 mm最大线性误差 (EL):0.3906%
湿度敏感等级:1位数:12
功能数量:1端子数量:8
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:COMMERCIAL
座面最大高度:1.45 mm标称安定时间 (tstl):12 µs
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.65 mm
Base Number Matches:1

AD5320BRM 数据手册

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(V = +2.7 V to +5.5 V; R = 2 kto GND; C = 200 pF to GND; all specifications  
DD  
L
L
T
MIN to TMAX unless otherwise noted)  
AD5320–SPECIFICATIONS  
B Version1  
Typ  
P aram eter  
Min  
Max  
Unit  
Conditions/Com m ents  
STATIC PERFORMANCE2  
Resolution  
Relative Accuracy  
Differential Nonlinearity  
Zero Code Error  
12  
Bits  
LSB  
LSB  
mV  
±16  
±1  
+40  
See Figure 2.  
Guaranteed Monotonic by Design. See Figure 3.  
All Zeroes Loaded to DAC Register. See Figure 6.  
All Ones Loaded to DAC Register. See Figure 6.  
+5  
Full-Scale Error  
Gain Error  
Zero Code Error Drift  
Gain Temperature Coefficient  
–0.15  
–1.25 % of FSR  
±1.25 % of FSR  
µV/°C  
–20  
–5  
ppm of FSR/°C  
OUTPUT CHARACTERISTICS3  
Output Voltage Range  
Output Voltage Settling Time  
0
VDD  
10  
V
µs  
8
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex).  
RL = 2 k; 0 pF < CL < 200 pF. See Figure 16.  
RL = 2 k; CL = 500 pF  
12  
1
µs  
V/µs  
pF  
Slew Rate  
Capacitive Load Stability  
470  
1000  
20  
0.5  
1
RL =  
pF  
RL = 2 kΩ  
Digital-to-Analog Glitch Impulse  
Digital Feedthrough  
nV-s  
nV-s  
1 LSB Change Around Major Carry. See Figure 19.  
DC Output Impedance  
Short Circuit Current  
50  
20  
2.5  
5
mA  
mA  
µs  
VDD = +5 V  
VDD = +3 V  
Power-Up Time  
Coming Out of Power-Down Mode. VDD = +5 V  
Coming Out of Power-Down Mode. VDD = +3 V  
µs  
LOGIC INPUTS3  
Input Current  
VINL, Input Low Voltage  
±1  
0.8  
0.6  
µA  
V
V
VDD = +5 V  
VDD = +3 V  
VDD = +5 V  
VDD = +3 V  
V
INL, Input Low Voltage  
VINH, Input High Voltage  
VINH, Input High Voltage  
Pin Capacitance  
2.4  
2.1  
V
V
pF  
3
POWER REQUIREMENTS  
VDD  
2.7  
5.5  
V
IDD (Normal Mode)  
VDD = +4.5 V to +5.5 V  
DAC Active and Excluding Load Current  
VIH = VDD and VIL = GND  
VIH = VDD and VIL = GND  
140  
115  
250  
200  
µA  
µA  
V
DD = +2.7 V to +3.6 V  
IDD (All Power-Down Modes)  
VDD = +4.5 V to +5.5 V  
VDD = +2.7 V to +3.6 V  
0.2  
0.05  
1
1
µA  
µA  
VIH = VDD and VIL = GND  
VIH = VDD and VIL = GND  
POWER EFFICIENCY  
IOUT/IDD  
93  
%
ILOAD = 2 mA. VDD = +5 V  
NOTES  
1Temperature ranges are as follows: B Version: –40°C to +105°C.  
2Linearity calculated using a reduced code range of 48 to 4047. Output unloaded.  
3Guaranteed by design and characterization, not production tested.  
Specifications subject to change without notice.  
–2–  
REV. B  

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