Datasheet > AD5320_05

AD5320_05

更新时间： 2022-04-12 00:26:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	410K
描述
2.7 V to 5.5 V, 140 Î¼A, Rail-to-Rail Output 12-Bit DAC in an SOT-23

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AD5320_05 数据手册

AD5320

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

DIN

AD5320

SYNC

SCLK

DIN

OUT

TOP VIEW

AD5320

SCLK

GND

(Not to Scale)

TOP VIEW

OUT

SYNC

(Not to Scale)

NC = NO CONNECT

Figure 4. MSOP Pin Configuration

Figure 3. SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

SOT-23

Pin No.

MSOP

Pin No.

Mnemonic

Description

V_OUT

GND

V_DD

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and V_DDshould be decoupled

to GND.

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input.

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz.

Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.

When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges

of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high

before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is

ignored by the DAC.

SCLK

SYNC

2, 3

No Connect.

Rev. C | Page 6 of 20

1...3 4 567 8 9...20

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