Datasheet > AD5315BRMZ-REEL71

AD5315BRMZ-REEL71

更新时间： 2022-04-21 15:34:55

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	565K
描述
2.5 V to 5.5 V, 500 Î¼A, 2-Wire Interface Interface

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AD5305/AD5315/AD5325

AC CHARACTERISTICS

V_DD= 2.5 V to 5.5 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND, all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

A, B Version¹

Parameter^{2, 3}

Min

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time

AD5305

AD5315

V_REF= V_DD= 5 V

μs

¼ scale to ¾ scale change (0×40 to 0×C0)

¼ scale to ¾ scale change (0×100 to 0×300)

¼ scale to ¾ scale change (0×400 to 0×C00)

AD5325

Slew Rate

0.7

V/μs

nV-s

kHz

Major-Code Transition Glitch Energy

Digital Feedthrough

Digital Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB change around major carry

200

−70

V_REF= 2 V 0.1 V p-p

V_REF= 2.5 V 0.1 V p-p, frequency = 10 kHz

¹Temperature range (A, B version): −40°C to +105°C; typical at +25°C.

²Guaranteed by design and characterization, not production tested.

³See the Terminology section.

TIMING CHARACTERISTICS

V_DD= 2.5 V to 5.5 V, all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter^{1, 2}

ꢀimit at T_MIN, T_MAX(A, B Version)

Unit

Conditions/Comments

f_SCL

t₁

t₂

t₃

t₄

400

2.5

0.6

1.3

0.6

100

0.9

0.6

1.3

300

kHz max

μs min

ns min

μs max

μs min

ns max

ns min

ns max

ns min

ns max

ns min

pF max

SCL clock frequency

SCL cycle time

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD,STA, start/repeated start condition hold time

t_SU,DAT, data setup time

t_HD,DAT, data hold time

t₅

t₆

t_HD,DAT, data hold time

t₇

t₈

t₉

t₁₀

t_SU,STA, setup time for repeated start

t_SU,STO, stop condition setup time

t_BUF, bus-free time between a stop and a start condition

t_R, rise time of SCL and SDA when receiving

t_R, rise time of SCL and SDA when receiving (CMOS compatible)

t_F, fall time of SDA when transmitting

t_F, fall time of SDA when receiving (CMOS compatible)

t_F, fall time of SCL and SDA when receiving

t_F, fall time of SCL and SDA when transmitting

Capacitive load for each bus line

t₁₁

250

300

20 + 0.1 C_B

400

C_B

¹See Figure 2.

²Guaranteed by design and characterization; not production tested.

³A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V_IHmin of the SCL signal) in order to bridge the undefined region of SCL’s

falling edge.

⁴C_Bis the total capacitance of one bus line in pF. t_Rand t_Fmeasured between 0.3 V_DDand 0.7 V_DD

Rev. G | Page 5 of 24

1 2 3 456 7 8...24

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