Datasheet > AD5308_11

AD5308_11

更新时间： 2022-04-11 23:58:21

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	408K
描述
2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

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AD5308_11 数据手册

AD5308/AD5318/AD5328

Table 3. Timing Characteristics^{1, 2, 3}

A, B Version

Parameter

ꢀimit at T_MIN, T_MAX

Unit

Conditions/Comments

t₁

t₂

t₃

t₄

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time; temperature range (A, B

verstion): −40°C to +105°C

ns min

SYNC to SCLK falling edge setup time; temperature range (A, B

verstion): −40°C to +125°C

t₅

t₆

t₇

4.5

ns min

Data set up time

Data hold time

SCLK falling edge to SYNC rising edge

t₈

Minimum SYNC high time

t₉

LDAC pulse width

t₁₀

t₁₁

SCLK falling edge to LDAC rising edge

SCLK falling edge to LDAC falling edge

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 2.

t₁

SCLK

t₂

t₃

t₇

t₈

t₄

t₆

SYNC

DIN

t₅

DB15

DB0

t₉

t₁₁

LDAC

t₁₀

LDAC

NOTES

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

Figure 2. Serial Interface Timing Diagram

Rev. F | Page 6 of 28

1...3 4 567 8 9...28

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