Datasheet > AD5301BRMZ-REEL71

AD5301BRMZ-REEL71

更新时间： 2022-04-12 13:54:50

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	429K
描述
2.5 V to 5.5 V, 120 Î¼A, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs

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AD5301BRMZ-REEL71 数据手册

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AD5301/AD5311/AD5321

SPECIFICATIONS

V_DD= 2.5 V to 5.5 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

B Version¹

Parameter²

Min

Typ

Max

Unit

Conditions/Comments

DC PERFORMANCE^{3, 4}

AD5301

Resolution

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5311

0.15

0.02

0.25

Guaranteed monotonic by design over all codes.

Resolution

0.5

0.05

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5321

0.5

Resolution

Bits

Relative Accuracy

Differential Nonlinearity

Zero-Code Error

Full-Scale Error

Gain Error

Zero-Code Error Drift⁵

Gain Error Drift⁵

0.3

1ꢀ

0.8

1.25

LSB

% of FSR

μV/°C

Guaranteed monotonic by design over all codes.

All zeros loaded to DAC, see Figure 12.

All ones loaded to DAC, see Figure 12.

0.15

–20

−5

ppm of FSR/°C

OUTPUT CHARACTERISTICS⁵

Minimum Output Voltage

Maximum Output Voltage

DC Output Impedance

Short-Circuit Current

0.001

V_DD− 0.001

2.5

ꢀ

μs

This is a measure of the minimum and maximum

drive capability of the output amplifier.

V_DD= 5 V.

V_DD= 3 V.

Power-Up Time

Coming out of power-down mode. V_DD= 5 V.

Coming out of power-down mode. V_DD= 3 V.

LOGIC INPUTS (A0, A1, PD)⁵

Input Current

0.8

μA

Input Low Voltage, V_IL

V_DD= 5 V 10%.

V_DD= 3 V 10%.

V_DD= 2.5 V.

0.ꢀ

0.5

Input High Voltage, V_IH

2.4

2.1

2.0

V_DD= 5 V 10%.

V_DD= 3 V 10%.

V_DD= 2.5 V.

Pin Capacitance

LOGIC INPUTS (SCL, SDA)⁵

ꢀ

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current, I_IN

Input Hysteresis, V_HYST

Input Capacitance, C_IN

Glitch Rejection^ꢀ

0.7 × V_DD

−0.3

V_DD+ 0.3

+0.3 × V_DD

μA

V_IN= 0 V to V_DD.

0.05 × V_DD

Pulse width of spike suppressed.

Rev. B | Page 3 of 24

1 234 5 6 7...24

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