PRELIMINARY TECHNICAL DATA
AD5280/AD5282
9
AD0
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
TABLE 2: AD5282 PIN Function Descriptions
Pin
1
2
Name
O1
A1
Description
Logic Output terminal O1
Resistor terminal A1
Wiper terminal W1
10
AD1
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Common Ground
Negative power supply, specified for
3
W1
4
5
B1
VDD
Resistor terminal B1
Positive power supply, specified for
11
12
GND
VSS
operation from +5 to +15V.
Active Low, Asynchronous connection of
the wiper W to terminal B, and open
circuit of terminal A. RDAC register
contents unchanged.
operation from 0 to -5V
Logic Supply Voltage, needs to be same
voltage as the digital logic controlling the
AD5282.
Resistor terminal B2
Wiper terminal W2
6
SHDN
13
VL
14
15
16
B2
W2
A2
7
8
SCL
SDA
Serial Clock Input
Serial Data Input/Output
Resistor terminal A2
t8
SDA
t1
t6
t8
t9
SCL
t2
t3
t4
t5
t7
t10
P
S
Sr
P
Figure 1. Detail Timing Diagram
Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format:
S
0
1
0
1
1
A
D
1
A
D
0
R/
W
A
R
S
S
D
O
1
O
2
X
X
X
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
P
A/
B
Slave Address Byte
Instruction Byte
Data Byte
Where:
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W= Read Enable at High and Write Enable at Low
A/B = RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2
SD = Shutdown, same as SHDN pin operation except inverse logic
O2, O1 = Output logic pin latched values
AD1, AD0 = Package pin programmable address bits
D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits
9
9
9
1
1
1
0
SCL
SDA
1
AD1
AD0
R/W
A/B
RS
SD
O1
O2
X
D7
D6
D5
D4
D1
D0
1
X
X
D3
D2
1
0
ACK. BY
AD5280
ACK. BY
AD5280
ACK. BY
AD5280
START BY
MASTER
FRAME 1
Slave Address Byte
FRAME
Instruction Byte
2
FRAME 3
Data Byte
Figure 2. Writing to the RDAC Register
REV PrE 12 MAR 02
5
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com