PRELIMINARY TECHNICAL DATA
Quad +15V Digital Potentiometers
AD5263
SPI Compatible Digital Interface (DIS=’0’)
1
0
SDI
Ax or Dx
A'x or D'x
Ax or Dx
tDS
(Data In)
tDH
TABLE IA: SPI 10-Bit Serial-Data Word
Format
1
0
SDO
A'x or D'x
(Data Out)
tPD_MAX
ADDR
B9
DATA
tCH
B8 B7 B6 B5 B4 B3 B2 B1 B0
1
0
tCS1
CLK
CS
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
27
LSB
20
tCSH0
tCSH1
tCL
29
1
0
tCSS
tCSW
tS
1
V
VOUT
DD
0V
SDI
A1 A0 D7 D6 D5 D4 D3
D1 D0
D2
±1 LSB
0
1
±1 LSB ERROR BAND
CLK
Figure 1B. Detail SPI Timing Diagram
0
1
RDAC REGISTER LOAD
CS
0
1
VOUT
0
Figure 1A. SPI Timing Diagram
I2C Compatible Digital Interface (DIS=’1’)
TABLE IIA: I2C Write Mode Data Word Format
S
0
1
0
1
1
A
D
1
A
D
0
A
X
A
1
A
0
R
S
S
D
O
1
O
2
X
A
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
P
W
Slave Address Byte
Instruction Byte
Data Byte
TABLE IIB: I2C Read Mode Data Word Format:
S
0
1
0
1
1
0
A
D
0
A
D
7
D
8
D
5
D
4
D
3
D
2
D
1
D
0
P
R
Slave Address Byte
Data Byte
S = Start Condition
P = Stop Condition
A = Acknowledge
SD = Shutdown active high, ties wiper (A1, A0) to terminal A,
opens terminal B, RDAC register contents are not disturbed. To exit
shutdown a command SD = ‘0’ must be executed for each RDAC
(A1, A0).
W = Write = ‘0’
AD1, AD0 = Package pin programmable address bits, Must match
with the logic states at pins AD1, AD0
R = Read = ‘1’
A1, A0 = RDAC sub address select
D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits
X = Don’t Care
RS = Software Reset wiper (A1, A0) to mid scale position
t8
SDA
t1
t6
t8
t9
SCL
t2
t3
t4
t5
t7
t10
P
S
Sr
P
Figure 2. I2C Compatible Detail Timing Diagram
08 AUG ’02, REV PrD
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