PRELIMINARY TECHNICAL DATA
Quad +15V Digital Potentiometers
AD5263
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VL = +5V,
VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12)
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay13
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCH,tCL
tDS
tDH
Clock level high or low
50
20
20
1
20
40
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPD
RL = 1KΩ, CL < 20pF
150
tCSS
tCSW
tRS
tCSH
tCS1
10
I2C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
fSCL
t1
t2
t3
t4
0
400
0.9
KHz
µs
µs
µs
µs
µs
µs
ns
tBUF Bus free time between STOP & START
tHD;STA Hold Time (repeated START)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time For START Condition t5
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of both SDA & SCL signals
tR Rise Time of both SDA & SCL signals t9
1.3
0.6
1.3
0.6
0.6
0
After this period the first clock pulse is generated
t6
t7
t8
100
300
300
ns
ns
tSU;STO Setup time for STOP Condition
t10
0.6
µs
NOTES:
1.
2.
Typicals represent average readings at +25°C and VDD = +5V, VSS = -5V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+5V, VSS=-5V.
3.
4.
VAB = VDD, Wiper (VW) = No connect
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
5.
6.
7.
8.
9.
Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic.
P
is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.
DISS
DD DD
10. All dynamic characteristics use VDD = +5V, VSS = -5V, VL = +5V.
11. Measured at a V pin where an adjacent V pin is making a full-scale voltage change.
W
W
12. See timing diagram for location of measured values. All input control voltages are specified with t =t =2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics
R
F
are measured using VL = +5V.
13. Propagation delay depends on value of VDD, RL, and CL see applications text.
14. The AD5260/AD5262 contains 1,968 transistors. Die Size: 89mil x 105mil, 9,345sq. mil.
08 AUG ’02, REV PrD
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