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AD5262BRUZ20-RL7 PDF预览

AD5262BRUZ20-RL7

更新时间： 2024-01-08 14:09:20
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
24页 610K
描述
1-/2-Channel 15 V Digital Potentiometer

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AD5262BRUZ20-RL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknown风险等级：5.76
Is Samacsys：N其他特性：IT CAN ALSO OPERATE FROM A SINGLE 4.5V TO 16.5V SUPPLY; ALSO REQUIRES A +2.7V TO +5.5V LOGIC SUPPLY
标称带宽：0.31 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
湿度敏感等级：1标称负供电电压：-5 V
功能数量：2位置数：256
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL电阻定律：LINEAR
最大电阻容差：30%最大电阻器端电压：5 V
最小电阻器端电压：-5 V座面最大高度：1.2 mm
标称供电电压：5 V表面贴装：YES
标称温度系数：35 ppm/ °C温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40标称总电阻：20000 Ω
宽度：4.4 mmBase Number Matches：1

AD5262BRUZ20-RL7 数据手册

 浏览型号AD5262BRUZ20-RL7的Datasheet PDF文件第1页浏览型号AD5262BRUZ20-RL7的Datasheet PDF文件第2页浏览型号AD5262BRUZ20-RL7的Datasheet PDF文件第3页浏览型号AD5262BRUZ20-RL7的Datasheet PDF文件第5页浏览型号AD5262BRUZ20-RL7的Datasheet PDF文件第6页浏览型号AD5262BRUZ20-RL7的Datasheet PDF文件第7页 
AD5260/AD5262  
Parameter  
DYNAMIC CHARACTERISTICS6, 10  
Symbol  
Conditions  
Min  
Typ1  
Max Unit  
Bandwidth –3 dB  
Total Harmonic Distortion  
BW  
THDW  
RAB = 20 kΩ/50 kΩ/200 kΩ  
VA = 1 VRMS, VB = 0 V, f = 1 kHz,  
RAB = 20 kΩ  
310/130/30  
0.014  
kHz  
%
VW Settling Time  
Crosstalk11  
tS  
VA = +5 V, VB = −5 V, ±1 LSB  
error band, RAB = 20 kΩ  
VA = VDD, VB = 0 V, measure VW  
with adjacent RDAC making  
full-scale code change (AD5262  
only)  
5
1
μs  
CT  
nV-sec  
Analog Crosstalk  
CTA  
VA1 = VDD, VB1 = 0 V, measure VW1  
with VW2 = 5 V p-p at f = 10 kHz,  
RAB = 20 kΩ/200 kΩ (AD5262  
only)  
–64  
13  
dB  
Resistor Noise Voltage  
INTERFACE TIMING CHARACTERISTICS6, 12  
Clock Frequency  
Input Clock Pulse Width  
Data Setup Time  
eN_WB  
RWB = 20 kΩ, f = 1 kHz  
nV/√Hz  
Specifications apply to all parts  
fCLK  
tCH, tCL  
tDS  
tDH  
tPD  
25  
MHz  
ns  
ns  
ns  
ns  
Clock level high or low  
RL = 1 kΩ, CL< 20 pF  
20  
10  
10  
1
Data Hold Time  
CLK to SDO Propagation Delay13  
160  
CS  
CS  
tCSS  
5
ns  
Setup Time  
tCSW  
tRS  
tCSH  
tCS1  
20  
50  
0
ns  
ns  
ns  
ns  
High Pulse Width  
Reset Pulse Width  
CS  
CLK Fall to Rise Hold Time  
CS  
10  
Rise to Clock Rise Setup  
1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V.  
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and  
VSS = −5V.  
3 VAB = VDD, wiper = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.  
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.  
8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.  
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V.  
11 Measured at VW where an adjacent VW is making a full-scale voltage change.  
12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.  
Switching characteristics are measured using VL = 5 V.  
13 Propagation delay depends on value of VDD, RL, and CL.  
Rev. A | Page 4 of 24  
1234567...24

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