AD5259
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V 10% or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING
CHARACTERISTICS1
SCL Clock Frequency
tBUF Bus Free Time Between Stop
and Start
fSCL
t1
±
1.3
4±±
kHz
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
generated.
±.6
μs
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated
Start Condition
t3
t4
t5
1.3
±.6
±.6
μs
μs
μs
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and
SCL Signals
tR Rise Time of Both SDA and
SCL Signals
t6
t7
t8
±
1±±
±.9
μs
ns
ns
3±±
3±±
t9
ns
tSU;STO Setup Time for Stop Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at
Power On2
t1±
±.6
μs
ms
μs
tEEMEM_STORE
26
3±±
tEEMEM_RESTORE1 VDD rise time dependent. Measure without
decoupling capacitors at VDD and GND.
EEPROM Data Restoring Time upon
tEEMEM_RESTORE2 VDD = 5 V.
3±±
54±
μs
μs
Restore Command2
EEPROM Data Rewritable Time3
FLASH/EE MEMORY RELIABILITY
Endurance4
tEEMEM_REWRITE
1±±
7±±
1±±
kCycles
Years
Data Retention5
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 1±±,±±± cycles per JEDEC Std. 22 method A117, and is measured at –4±°C, +25°C, and +85°C; typical endurance at +25°C is 7±±,±±± cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of ±.6 eV derates
with junction temperature.
t2
t8
t6
t9
SCL
SDA
t10
t4
t7
t5
t2
t3
t9
t8
t1
P
S
S
P
Figure 4. I2C Interface Timing Diagram
Rev. A | Page 5 of 24