Datasheet > AD5254BRU10-RL7

AD5254BRU10-RL7

更新时间： 2024-02-15 10:06:54

品牌	Logo	应用领域
亚德诺 - ADI		电位器存储
页数	文件大小	规格书
28页	1160K
描述
Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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中文翻译

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数据手册
替代型号

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AD5254BRU10-RL7 数据手册

AD5253/AD5254

+5V

× 4

AD1

AD0

2 × 4

DECODER

+5V

× 4

AD1

AD0

Figure 39. Maximum Terminal Voltages Set by V_DDand V_SS

2 × 4

DECODER

POWER-UP AND POWER-DOWN SEQUENCES

Since the ESD protection diodes limit the voltage compliance at

terminals A, B, and W (Figure 39), it is important to power

V_DD/V_SSbefore applying any voltage to terminals A, B, and W.

Otherwise, the diodes are forward-biased such that V_DD/V_SSare

powered unintentionally and may affect the rest of the user’s

circuit. Similarly, V_DD/V_SSshould be powered down last. The

+5V

2 × 4

DECODER

× 4

ideal power-up sequence is in the following order: GND, V_DD

V_SS, digital inputs, and V_A/V_B/V_W. The order of powering V_A, V_B,

V_W, and the digital inputs is not important, as long as they are

powered after V_DD/V_SS.

AD1

AD0

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to employ a compact, minimum

lead-length layout design. The leads to the input should be as

direct as possible, with a minimum conductor length. Ground

paths should have low resistance and low inductance.

+5V

2 × 4

DECODER

× 4

AD1

AD0

Similarly, it is also good practice to bypass the power supplies

with quality capacitors. Low ESR (equivalent series resistance)

1 µF to 10 µF tantalum or electrolytic capacitors should be

applied at the supplies to minimize any transient disturbance

and filter low frequency ripple. Figure 40 illustrates the basic

supply-bypassing configuration for the AD5253/AD5254.

Figure 38. Four Devices with AD1 and AD0 of 00

TERMINAL VOLTAGE OPERATION RANGE

AD5253/AD5254

The AD5253/AD5254 are designed with internal ESD diodes

for protection; these diodes also set the boundary of the

terminal operating voltages. Positive signals present on terminal

A, B, or W that exceed V_DDare clamped by the forward biased

diode. Similarly, negative signals on terminal A, B, or W that are

more negative than V_SSare also clamped (see Figure 39). In

practice, users should not operate V_AB, V_WA, and V_WBto be

higher than the voltage across V_DD-to-V_SS, but V_AB, V_WA, and V_WB

have no polarity constraint.

10µF

0.1µF

10µF

GND

Figure 40. Power Supply Bypassing

The ground pin of the AD5253/AD5254 is used primarily as a

digital ground reference. To minimize the digital ground

bounce, the AD5253/AD5254 ground terminal should be joined

remotely to the common ground (see Figure 40).

Rev. 0 | Page 22 of 28

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AD5254BRU10-RL7 替代型号

型号	品牌	替代类型	描述	数据表
AD5254BRU10	ADI	完全替代	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ10-RL7	ADI	类似代替	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ10	ADI	类似代替	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

与AD5254BRU10-RL7相关器件

型号	品牌	获取价格	描述	数据表
AD5254BRU1-RL7	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRU50	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRU50-RL7	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ1	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ10	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ100	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ100-RL7	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ10-RL7	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ1-RL7	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5254BRUZ50	ADI	获取价格	Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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