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AD5253BRUZ1 PDF预览

AD5253BRUZ1

更新时间： 2024-02-29 11:27:43
品牌 Logo 应用领域
亚德诺 - ADI 电位器存储
页数 文件大小 规格书
32页 576K
描述
Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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AD5253BRUZ1 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.99
其他特性：NONVOLATILE MEMORY; DEVICE SUPPORTS DUAL SUPPLY OPERATION标称带宽：4 kHz
控制接口：2-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：6.5 mm湿度敏感等级：1
标称负供电电压：-2.5 V功能数量：4
位置数：64端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：2.75 V最小电阻器端电压：-2.25 V
座面最大高度：1.2 mm子类别：Digital Potentiometers
标称供电电压：2.5 V表面贴装：YES
技术：CMOS标称温度系数：650 ppm/ °C
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
标称总电阻：1000 Ω宽度：4.4 mm
Base Number Matches：1

AD5253BRUZ1 数据手册

 浏览型号AD5253BRUZ1的Datasheet PDF文件第1页浏览型号AD5253BRUZ1的Datasheet PDF文件第2页浏览型号AD5253BRUZ1的Datasheet PDF文件第3页浏览型号AD5253BRUZ1的Datasheet PDF文件第5页浏览型号AD5253BRUZ1的Datasheet PDF文件第6页浏览型号AD5253BRUZ1的Datasheet PDF文件第7页 
AD5253/AD5254  
Data Sheet  
Parameter  
Symbol  
VIH  
Conditions  
Min  
Typ 1  
Max  
Unit  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
VDD = 5 V, VSS = 0 V  
2.4  
V
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V 2.1  
VDD = 5 V, VSS = 0 V  
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V  
V
V
V
Input Logic Low  
VIL  
0.8  
0.6  
Output Logic High (SDA)  
Output Logic Low (SDA)  
WP Leakage Current  
A0 Leakage Current  
Input Leakage Current  
(Other than WP and A0)  
Input Capacitance5  
VOH  
VOL  
IWP  
IA0  
II  
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V  
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V  
WP = VDD  
4.9  
V
V
µA  
µA  
µA  
0.4  
8
A0 = GND  
VIN = 0 V or VDD  
3
1
CI  
5
pF  
POWER SUPPLIES  
Single-Supply Power Range  
Dual-Supply Power Range  
Positive Supply Current  
Negative Supply Current  
VDD  
VDD/VSS  
IDD  
VSS = 0 V  
2.7  
2.25  
5.5  
2.75  
15  
–15  
V
V
µA  
µA  
VIH = VDD or VIL = GND  
VIH = VDD or VIL = GND, VDD = 2.5 V,  
VSS = –2.5 V  
5
–5  
ISS  
EEMEM Data Storing Mode Current IDD_STORE  
VIH = VDD or VIL = GND  
VIH = VDD or VIL = GND  
35  
2.5  
mA  
mA  
EEMEM Data Restoring Mode  
IDD_RESTORE  
Current6  
Power Dissipation7  
PDISS  
PSS  
VIH = VDD = 5 V or VIL = GND  
ΔVDD = 5 V 10%  
0.075  
mW  
Power Supply Sensitivity  
−0.025 +0.010 +0.025 %/%  
ΔVDD = 3 V 10%  
–0.04  
+0.02  
+0.04  
%/%  
DYNAMIC CHARACTERISTICS5, 8  
Bandwidth –3 dB  
Total Harmonic Distortion  
VW Settling Time  
BW  
THD  
tS  
RAB = 1 kΩ  
VA =1 V rms, VB = 0 V, f = 1 kHz  
VA = VDD, VB = 0 V  
RWB = 500 Ω, f = 1 kHz  
(thermal noise only)  
4
MHz  
%
µs  
0.05  
0.2  
3
Resistor Noise Voltage  
eN_WB  
nV/√Hz  
Digital Crosstalk  
Analog Coupling  
CT  
VA = VDD, VB = 0 V, measure VW with  
adjacent RDAC making full-scale  
change  
Signal input at A0 and measure the  
output at W1, f = 1 kHz  
–80  
–72  
dB  
dB  
CAT  
1 Typical values represent average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the  
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at VDD = 2.7 V,  
IW = VDD/R for both VDD = 3 V and VDD = 5 V.  
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.  
5 Guaranteed by design and not subject to production test.  
6 Command 0 NOP should be activated after Command 1 to minimize IDD_RESTORE current consumption.  
7 PDISS is calculated from IDD × VDD = 5 V.  
8 All dynamic characteristics use VDD = 5 V.  
Rev. C | Page 4 of 32  
 
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