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AD5251BRUZ100-RL7 PDF预览

AD5251BRUZ100-RL7

更新时间： 2024-01-28 23:53:47
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计存储电阻器光电二极管PC
页数 文件大小 规格书
28页 575K
描述
Dual 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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AD5251BRUZ100-RL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:11.142是否无铅：含铅
是否Rohs认证：符合生命周期：Obsolete
包装说明：TSSOP, TSOP14,.26,26针数：14
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.36
Samacsys Confidence：Samacsys Status：Released
Schematic Symbol：https://componentsearchengine.com/symbol.php?partID=578414PCB Footprint：https://componentsearchengine.com/footprint.php?partID=578414
Samacsys PartID：578414Samacsys Image：https://componentsearchengine.com/Images/9/AD5251BRUZ100-RL7.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/AD5251BRUZ100-RL7.jpgSamacsys Pin Count：14
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Other
Samacsys Footprint Name：SOP65P640X120-14NSamacsys Released Date：2017-01-11 11:21:59
Is Samacsys：N标称带宽：0.04 kHz
控制接口：2-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：R-PDSO-G14长度：5 mm
功能数量：1位置数：64
端子数量：14最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSOP14,.26,26
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电阻定律：LINEAR最大电阻容差：20%
最大电阻器端电压：2.75 V最小电阻器端电压：-2.25 V
座面最大高度：1.2 mm最大压摆率：0.015 mA
标称供电电压：2.5 V表面贴装：YES
技术：CMOS标称温度系数：650 ppm/ °C
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
标称总电阻：100000 Ω宽度：4.4 mm
Base Number Matches：1

AD5251BRUZ100-RL7 数据手册

 浏览型号AD5251BRUZ100-RL7的Datasheet PDF文件第1页浏览型号AD5251BRUZ100-RL7的Datasheet PDF文件第2页浏览型号AD5251BRUZ100-RL7的Datasheet PDF文件第3页浏览型号AD5251BRUZ100-RL7的Datasheet PDF文件第5页浏览型号AD5251BRUZ100-RL7的Datasheet PDF文件第6页浏览型号AD5251BRUZ100-RL7的Datasheet PDF文件第7页 
AD5251/AD5252  
Data Sheet  
Parameter  
Symbol  
Conditions  
Min  
Typ 1  
Max  
Unit  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
VIH  
VDD = 5 V, VSS = 0 V  
2.4  
V
VDD/VSS = 2.7 V/0 V or VDD/VSS = 2.5 V 2.1  
VDD = 5 V, VSS = 0 V  
V
V
V
V
µA  
µA  
µA  
Input Logic Low  
VIL  
VOH  
VOL  
IWP  
IA0  
II  
0.8  
Output Logic High (SDA)  
Output Logic Low (SDA)  
WP Leakage Current  
A0 Leakage Current  
Input Leakage Current  
(Other than WP and A0)  
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V  
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V  
WP = VDD  
4.9  
0.4  
8
A0 = GND  
VIN = 0 V or VDD  
3
1
Input Capacitance5  
CI  
5
pF  
POWER SUPPLIES  
Single-Supply Power Range  
Dual-Supply Power Range  
Positive Supply Current  
Negative Supply Current  
VDD  
VDD/VSS  
IDD  
VSS = 0 V  
2.7  
2.25  
5.5  
2.75  
15  
–15  
V
V
µA  
µA  
VIH = VDD or VIL = GND  
VIH = VDD or VIL = GND, VDD = 2.5 V,  
VSS = –2.5 V  
5
–5  
ISS  
EEMEM Data Storing Mode Current  
IDD_STORE  
IDD_RESTORE  
VIH = VDD or VIL = GND  
VIH = VDD or VIL = GND  
35  
2.5  
mA  
mA  
EEMEM Data Restoring Mode  
Current6  
Power Dissipation7  
PDISS  
PSS  
VIH = VDD = 5 V or VIL = GND  
ΔVDD = 5 V 10%  
0.075  
mW  
Power Supply Sensitivity  
−0.025 +0.010 +0.025 %/%  
ΔVDD = 3 V 10%  
–0.04  
+0.02  
+0.04  
%/%  
DYNAMIC CHARACTERISTICS5, 8  
Bandwidth –3 dB  
Total Harmonic Distortion  
VW Settling Time  
BW  
THD  
tS  
RAB = 1 kΩ  
VA = 1 V rms, VB = 0 V, f = 1 kHz  
VA = VDD, VB = 0 V  
RWB = 500 Ω, f = 1 kHz  
(thermal noise only)  
4
MHz  
%
µs  
0.05  
0.2  
3
Resistor Noise Voltage  
eN_WB  
nV/√Hz  
Digital Crosstalk  
Analog Coupling  
CT  
VA = VDD, VB = 0 V, measure VW with  
adjacent RDAC making full-scale  
change  
Signal input at A1 and measure the  
output at W3, f = 1 kHz  
–80  
–72  
dB  
dB  
CAT  
1 Typical values represent average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the  
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD  
2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.  
=
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.  
5 Guaranteed by design and not subject to production test.  
6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption.  
7 PDISS is calculated from IDD × VDD = 5 V.  
8 All dynamic characteristics use VDD = 5 V.  
Rev. D | Page 4 of 28  
 
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