AD5251BRUZ100

更新时间： 2024-01-17 19:11:02

品牌	Logo	应用领域
亚德诺 - ADI		电位器存储
页数	文件大小	规格书
28页	575K
描述
Dual 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers

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AD5251BRUZ100 数据手册

AD5251/AD5252

Data Sheet

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

V_DD

V_DD/V_SS

I_DD

V_SS= 0 V

2.7

2.25

5.5

2.75

−15

µA

V_IH= V_DDor V_IL= GND

V_IH= V_DDor V_IL= GND, V_DD= 2.5 V,

V_SS= −2.5 V

−5

I_SS

EEMEM Data Storing Mode

Current

I_{DD_STORE}

V_IH= V_DDor V_IL= GND, T_A= 0°C to 105°C

EEMEM Data Restoring Mode

I_{DD_RESTORE}

V_IH= V_DDor V_IL= GND, T_A= 0°C to 105°C

2.5

Current⁶

Power Dissipation⁷

P_DISS

PSS

V_IH= V_DD= 5 V or V_IL= GND

ΔV_DD= 5 V 10%

ΔV_DD= 3 V 10%

0.075

Power Supply Sensitivity

−0.005 +0.002

−0.010 +0.002

+0.005 %/%

+0.010 %/%

DYNAMIC CHARACTERISTICS^{5, 8}

–3 dB Bandwidth

Total Harmonic Distortion

V_WSettling Time

THD_W

t_S

R_AB= 10 kΩ/50 kΩ/100 kΩ

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= V_DD, V_B= 0 V,

400/80/40

0.05

1.5/7/14

kHz

µs

R_AB= 10 kΩ/50 kΩ/100 kΩ

Resistor Noise Voltage

Digital Crosstalk

e_{N_WB}

R_AB= 10 kΩ/50 kΩ/100 kΩ,

code = midscale, f = 1 kHz

(thermal noise only)

V_A= V_DD, V_B= 0 V, measure V_Wwith

adjacent RDAC making full-scale

change

9/20/29

−80

nV/√Hz

C_T

Analog Coupling

C_AT

Signal input at A1 and measure

output at W3, f = 1 kHz

−72

¹Typical values represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V_DD= 2.7 V,

I_W= V_DD/R for both V_DD= 3 V and V_DD= 5 V.

³INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider, similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits

of 1 LSB maximum are guaranteed monotonic operating conditions.

⁴Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

⁶Command 0 NOP should be activated after Command 1 to minimize I_{DD_READ}current consumption.

⁷P_DISSis calculated from I_DD× V_DD= 5 V.

⁸All dynamic characteristics use V_DD= 5 V.

Rev. D | Page 6 of 28

1...3 4 567 8 9...28

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