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AD5243BRM2.5 PDF预览

AD5243BRM2.5

更新时间: 2024-02-06 08:52:41
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 1067K
描述
Dual 256-Position I2C Compatible Digital Potentiometer

AD5243BRM2.5 技术参数

Source Url Status Check Date:2013-05-01 14:56:11.03是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:3 X 4.90 MM, MO-187BA, MSOP-10
针数:10Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:8.12其他特性:IT ALSO OPERATES AT 5 V SUPPLY
标称带宽:4.8 kHz控制接口:2-WIRE SERIAL
转换器类型:DIGITAL POTENTIOMETERJESD-30 代码:S-PDSO-G10
JESD-609代码:e0长度:3 mm
湿度敏感等级:1功能数量:2
位置数:256端子数量:10
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3/5 V认证状态:Not Qualified
电阻定律:LINEAR最大电阻容差:55%
最大电阻器端电压:5.5 V最小电阻器端电压:
座面最大高度:1.1 mm子类别:Digital Potentiometers
标称供电电压:3 V表面贴装:YES
标称温度系数:35 ppm/ °C温度等级:AUTOMOTIVE
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20标称总电阻:2500 Ω
宽度:3 mmBase Number Matches:1

AD5243BRM2.5 数据手册

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AD5243/AD5248  
TIMING CHARACTERISTICS—ALL VERSIONS  
VDD = 5V 10ꢀ, or 3V 10ꢀ% VA = VDD% VB = 0 V% −40°C < TA < +125°C% unless otherwise noted.  
Table 3.  
Parameter  
Symbol  
Conditions  
Min  
Typ1 Max  
Unit  
I2C INTERFACE TIMING CHARACTERISTICS10 (Specifications Apply to All Parts)  
SCL Clock Frequency  
tBUF Bus Free Time between STOP and START  
tHD;STA Hold Time (Repeated START)  
fSCL  
t1  
t2  
0
1.3  
0.6  
400  
kHz  
µs  
µs  
After this period, the first clock pulse is  
generated.  
tLOW Low Period of SCL Clock  
tHIGH High Period of SCL Clock  
tSU;STA Setup Time for Repeated START Condition  
tHD;DAT Data Hold Time11  
tSU;DAT Data Setup Time  
tF Fall Time of Both SDA and SCL Signals  
tR Rise Time of Both SDA and SCL Signals  
tSU;STO Setup Time for STOP Condition  
t3  
t4  
t7  
t6  
tꢀ  
t8  
t9  
t10  
1.3  
0.6  
0.6  
µs  
µs  
µs  
µs  
ns  
ns  
ns  
µs  
0.9  
100  
0.6  
300  
300  
See notes at end of section.  
NOTES  
1 Typical specifications represent average readings at 27°C and VDD = 7 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.  
3 VAB = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
7 Resistor terminals A, B, W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
Measured at the A terminal. The A terminal is open circuited in shutdown mode.  
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
9All dynamic characteristics use VDD = 7 V.  
10See timing diagrams for locations of measured values.  
11The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.  
Rev. 0 | Page 7 of 20  
 

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