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AD5242BRUZ10-RL7 PDF预览

AD5242BRUZ10-RL7

更新时间： 2024-02-11 16:23:54
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 550K
描述
I2C-Compatible, 256-Position Digital Potentiometers

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AD5242BRUZ10-RL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknown风险等级：5.73
Is Samacsys：N其他特性：IT CAN ALSO OPERATE FROM A 3V NOM SINGLE SUPPLY OR +/-2.3V TO +/-2.7V DUAL SUPPLY
标称带宽：0.65 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
湿度敏感等级：1标称负供电电压：-2.5 V
功能数量：2位置数：256
端子数量：16最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL电阻定律：LINEAR
最大电阻容差：30%最大电阻器端电压：5.5 V
最小电阻器端电压：-2.3 V座面最大高度：1.2 mm
标称供电电压：2.5 V表面贴装：YES
标称温度系数：30 ppm/ °C温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40标称总电阻：10000 Ω
宽度：4.4 mmBase Number Matches：1

AD5242BRUZ10-RL7 数据手册

 浏览型号AD5242BRUZ10-RL7的Datasheet PDF文件第1页浏览型号AD5242BRUZ10-RL7的Datasheet PDF文件第2页浏览型号AD5242BRUZ10-RL7的Datasheet PDF文件第3页浏览型号AD5242BRUZ10-RL7的Datasheet PDF文件第5页浏览型号AD5242BRUZ10-RL7的Datasheet PDF文件第6页浏览型号AD5242BRUZ10-RL7的Datasheet PDF文件第7页 
AD5241/AD5242  
Parameter  
DYNAMIC CHARACTERISTICSꢁ, 7, 8  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
−3 dB Bandwidth  
BW_10 kΩ  
BW_100 kΩ  
BW_1 MΩ  
THDW  
RAB = 10 kΩ, code = 0x80  
RAB = 100 kΩ, code = 0x80  
RAB = 1 MΩ, code = 0x80  
VA = 1 V rms + 2 V dc,  
VB = 2 V dc, f = 1 kHz  
6ꢁ0  
69  
6
kHz  
kHz  
kHz  
%
Total Harmonic Distortion  
VW Settling Time  
0.00ꢁ  
tS  
VA = VDD, VB = 0 V, 1 LSB  
error band, RAB = 10 kΩ  
2
μs  
Resistor Noise Voltage  
eN_WB  
RWB = ꢁ kΩ, f = 1 kHz  
1ꢀ  
nV√Hz  
INTERFACE TIMING CHARACTERISTICS  
(APPLIES TO ALL PARTSꢁ, 9  
SCL Clock Frequency  
Bus Free Time Between Stop and Start, tBUF  
)
fSCL  
t1  
0
1.3  
ꢀ00  
kHz  
μs  
Hold Time (Repeated Start), tHD; STA  
t2  
After this period, the first 600  
clock pulse is generated  
ns  
Low Period of SCL Clock, tLOW  
High Period of SCL Clock, tHIGH  
Setup Time for Repeated Start Condition, tSU; STA  
Data Hold Time, tHD; DAT  
Data Setup Time, tSU; DAT  
Rise Time of Both SDA and SCL Signals, tR  
t3  
tꢀ  
tꢁ  
t6  
t7  
t8  
1.3  
0.6  
600  
μs  
μs  
ns  
ns  
ns  
ns  
ꢁ0  
900  
100  
300  
300  
Fall Time of Both SDA and SCL Signals, tF  
Setup Time for Stop Condition, tSU; STO  
t9  
t10  
ns  
1 Typicals represent average readings at 2ꢁ°C, VDD = ꢁ V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.  
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL  
specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.  
ꢀ Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
ꢁ Guaranteed by design, not subject to production test.  
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest  
bandwidth. The highest R value results in the minimum overall power consumption.  
8 All dynamic characteristics use VDD = ꢁ V.  
9 See timing diagram in Figure 3 for location of measured values.  
Rev. C | Page ꢀ of 20  
 
 
 
 
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