5秒后页面跳转
AD5241BR100 PDF预览

AD5241BR100

更新时间: 2024-01-25 03:38:47
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管
页数 文件大小 规格书
16页 348K
描述
I2C Compatible 256-Position Digital Potentiometers

AD5241BR100 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknown风险等级:5.33
其他特性:IT CAN ALSO OPERATE FROM A 3V NOM SINGLE SUPPLY OR +/-2.3V TO +/-2.7V DUAL SUPPLY标称带宽:0.069 kHz
控制接口:2-WIRE SERIAL转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm湿度敏感等级:1
标称负供电电压:-2.5 V功能数量:1
位置数:256端子数量:14
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240认证状态:COMMERCIAL
电阻定律:LINEAR最大电阻容差:50%
最大电阻器端电压:5.5 V最小电阻器端电压:-2.3 V
座面最大高度:1.75 mm标称供电电压:2.5 V
表面贴装:YES标称温度系数:30 ppm/ °C
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
标称总电阻:100000 Ω宽度:3.9 mm
Base Number Matches:1

AD5241BR100 数据手册

 浏览型号AD5241BR100的Datasheet PDF文件第1页浏览型号AD5241BR100的Datasheet PDF文件第2页浏览型号AD5241BR100的Datasheet PDF文件第4页浏览型号AD5241BR100的Datasheet PDF文件第5页浏览型号AD5241BR100的Datasheet PDF文件第6页浏览型号AD5241BR100的Datasheet PDF文件第7页 
AD5241/AD5242  
Parameter  
Symbol  
Conditions  
Min  
Typ1 Max  
Unit  
INTERFACE TIMING CHARACTERISTICS (Applies to all parts.5, 9  
)
SCL Clock Frequency  
fSCL  
t1  
0
1.3  
400  
kHz  
µs  
tBUF Bus Free Time between  
STOP and START  
tHD; STA Hold Time (Repeated START)  
t2  
After this period, the first clock  
pulse is generated.  
600  
ns  
t
LOW Low Period of SCL Clock  
t3  
t4  
1.3  
0.6  
µs  
µs  
tHIGH High Period of SCL Clock  
t
50  
SU; STA Setup Time for Repeated  
START Condition  
t5  
t6  
t7  
t8  
600  
100  
ns  
ns  
ns  
ns  
tHD; DAT Data Hold Time  
SU; DAT Data Setup Time  
900  
300  
300  
t
tR Rise Time of Both  
SDA and SCL Signals  
tF Fall Time of Both SDA and SCL Signals t9  
tSU; STO Setup Time for STOP Condition t10  
ns  
NOTES  
1Typicals represent average readings at 25°C, VDD = 5 V.  
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-  
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.  
3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 10.  
4Resistor terminals A, B, W have no limitations on polarity with respect to each other.  
5Guaranteed by design and not subject to production test.  
6PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
7Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-  
width. The highest R value results in the minimum overall power consumption.  
8All dynamic characteristics use VDD = 5 V.  
9See timing diagram for location of measured values.  
Specifications subject to change without notice.  
–3–  
REV. B  

与AD5241BR100相关器件

型号 品牌 描述 获取价格 数据表
AD5241BR100-REEL7 ADI I2C Compatible 256-Position Digital Potentiometers

获取价格

AD5241BR10-REEL7 ADI I2C Compatible 256-Position Digital Potentiometers

获取价格

AD5241BR1M ADI I2C Compatible 256-Position Digital Potentiometers

获取价格

AD5241BR1M-REEL7 ETC DIGITAL POTENTIOMETER|SOP|14PIN|PLASTIC

获取价格

AD5241BRU10 ADI I2C-Compatible, 256-Position Digital Potentiometers

获取价格

AD5241BRU100 ADI I2C-Compatible, 256-Position Digital Potentiometers

获取价格