Datasheet > AD5222BR100

AD5222BR100

更新时间： 2024-01-29 04:50:29

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		光电二极管商用集成电路
页数	文件大小	规格书
11页	856K
描述
2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO14, SOIC-14

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AD5222BR100 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	14
Reach Compliance Code：	unknown	风险等级：	5.61
其他特性：	CAN ALSO WORK WITH 5V SUPPLY	商用集成电路类型：	VOLUME CONTROL CIRCUIT
谐波失真：	0.005%	JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0	长度：	8.65 mm
湿度敏感等级：	1	信道数量：	2
功能数量：	1	端子数量：	14
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	认证状态：	COMMERCIAL
座面最大高度：	1.75 mm	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm	Base Number Matches：	1

AD5222BR100 数据手册

AD5222

OPERATION

U/D

The AD5222 provides a 128-position, digitally-controlled, variable

resistor (VR) device. Changing the VR settings is accomplished

by pulsing the CLK pin while CS is active low. The U/D (UP/

DOWN) control input pin controls the direction of the increment.

When the wiper hits the end of the resistor (Terminal A or B)

additional CLK pulses no longer change the wiper setting. The

wiper position is immediately decoded by the wiper decode logic

changing the wiper resistance. Appropriate debounce circuitry is

required when push-button switches are used to control the

count sequence and direction of count. The exact timing require-

ments are shown in Figure 2. The AD5222 powers ON in a

centered wiper position, exhibiting nearly equal resistances of

RDAC 1

U/D

COUNTER

DACSEL

MODE

RDAC 2

U/D

R_WAand R_WB

COUNTER

CLK

AD5222

Figure 30. Detailed Digital Logic Interface Circuit

UP/DOWN

COUNTER

DECODE

U/D

All digital inputs (CS, U/D, CLK, MODE, DACSEL) are

protected with a series input resistor and parallel Zener ESD

structure shown in Figure 31. All potentiometer terminal pins

(A, B, W) are protected from ESD as shown in Figure 32.

POR

MODE

DAC

SELECT

AND

UP/DOWN

COUNTER

DECODE

1k⍀

DACSEL

CLK

LOGIC

ENABLE

GND

Figure 31. Equivalent ESD Protection Digital Pins

Figure 29. Block Diagram

DIGITAL INTERFACING OPERATION

20⍀

A, B, W

The AD5222 contains a push-button controllable interface. The

active inputs are clock (CLK), CS and up/down (U/D). While

the MODE, and DACSEL pins control common updates or

individual updates. The negative-edge sensitive CLK input

requires clean transitions to avoid clocking multiple pulses into

the internal UP/DOWN counter register, Figure 30. Standard

logic families work well. If mechanical switches are used for

product evaluation a flip-flop or other suitable means should

debounce them. When CS is taken active low, the clock begins

to increment or decrement the internal up/down counter, depen-

dent upon the state of the U/D control pin. The UP/DOWN

counter value (D) starts at 40_Hat system power ON. Each new

CLK pulse will increment the value of the internal counter by

1 LSB until the full-scale value of 7F_His reached, as long as the

U/D pin is logic high. If the U/D pin is taken to logic low, the

counter will count down, stopping at code 00_H(zero-scale).

Additional clock pulses on the CLK pin are ignored when the

wiper is at either the 00_Hposition or the 7F_Hposition. The

detailed digital logic interface circuitry is shown in Figure 30.

Figure 32. Equivalent ESD Protection Analog Pins

RDAC

UP/DOWN

CNTR

DECODE

= R

/128

NOMINAL

Figure 33. AD5222 Equivalent RDAC Circuit

REV. 0

–8–

1...6 7 8910 11

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