AD5160
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ꢀ1%, or 3 V ꢀ1%ꢁ VA = VDDꢁ VB = 1 Vꢁ −41°C < TA < +ꢀ25°Cꢁ unless otherwise noted.
Table 2.
Parameter
Symbol Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1
−2
−15
±±.1
±±.25
+1
+2
+15
LSB
LSB
%
∆RAB/∆T VAB = VDD
,
45
5±
ppm/°C
Wiper = no connect
VDD = 5 V
Specifications apply to all VRs
Wiper Resistance
Potentiometer Divider Mode
Resolution
RW
12±
Ω
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature
Coefficient
DNL
INL
∆VW/∆T
−1
−1
±±.1
±±.3
15
+1
+1
LSB
LSB
ppm/°C
Code = ±x8±
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = ±xFF
Code = ±x±±
−3
±
−1
1
±
3
LSB
LSB
RESISTOR TERMINALS
Voltage Range5
VA,B,W
CA,B
GND
VDD
V
pF
Capacitance A, Capacitance B6
f = 1 MHz, measured to GND, code =
±x8±
f = 1 MHz, measured to GND, code =
±x8±
45
6±
1
Capacitance W6
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS
VA = VB = VDD/2
nA
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
μA
pF
±.8
VDD = 3 V
VDD = 3 V
VIN = ± V or 5 V
±.6
±1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipationꢀ
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
±.2
V
μA
mW
VIH = 5 V or VIL = ± V
VIH = 5 V or VIL = ± V, VDD = 5 V
∆VDD = +5 V ± 1±%, code = midscale
3
PSS
±±.±2
±±.±5 %/%
BW
THDW
RAB = 1± kΩ/5± kΩ/1±± kΩ, Code = ±x8±
VA = 1 V rms, VB = ± V, f = 1 kHz, RAB
1± kΩ
6±±/1±±/4±
±.±5
kHz
%
Total Harmonic Distortion
=
VW Settling Time (1± kΩ/5± kΩ/1±± kΩ)
Resistor Noise Voltage Density
tS
VA = 5 V, VB = ± V,
±1 LSB error band
RWB = 5 kΩ
2
9
μs
eN_WB
nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
± V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. B | Page 4 of 16
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