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AD5160BRJZ100-RL72 PDF预览

AD5160BRJZ100-RL72

更新时间: 2022-04-21 19:57:44
品牌 Logo 应用领域
亚德诺 - ADI 数字电位计
页数 文件大小 规格书
16页 467K
描述
256-Position SPI-Compatible Digital Potentiometer

AD5160BRJZ100-RL72 数据手册

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AD5160  
TIMING CHARACTERISTICS—ALL VERSIONS  
VDD = +5V ꢀ1%, or +3V ꢀ1%ꢁ VA = VDDꢁ VB = 1 Vꢁ –41°C < TA < +ꢀ25°Cꢁ unless otherwise noted.  
Table 3.  
Parameter  
SPI INTERFACE TIMING CHARACTERISTICS1, 2  
Symbol  
Conditions  
Min  
Typ1  
Max  
25  
Unit  
Specifications apply to all parts  
Clock Frequency  
Input Clock Pulse Width  
Data Setup Time  
fCLK  
tCH, tCL  
tDS  
MHz  
ns  
ns  
Clock level high or low  
2±  
5
Data Hold Time  
tDH  
5
ns  
CS Setup Time  
tCSS  
15  
4±  
±
ns  
CS High Pulse Width  
CLK Fall to CS Fall Hold Time  
CLK Fall to CS Rise Hold Time  
tCSW  
tCSH±  
tCSH1  
ns  
ns  
±
ns  
1 See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with tR = tF = 2 ns (1±% to 9±% of 3 V) and timed from a  
voltage level of 1.5 V.  
2 Guaranteed by design and not subject to production test.  
Rev. B | Page 5 of 16  
 
 

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