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AD5160BRJ100-R2 PDF预览

AD5160BRJ100-R2

更新时间： 2024-02-11 02:00:39
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
16页 775K
描述
256-Position SPI Compatible Digital Potentiometer

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AD5160BRJ100-R2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：LSSOP,针数：8
Reach Compliance Code：unknown风险等级：5.76
Is Samacsys：N其他特性：IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽：0.04 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：2.9 mm
湿度敏感等级：1功能数量：1
位置数：256端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：3 V最小电阻器端电压：
座面最大高度：1.45 mm标称供电电压：3 V
表面贴装：YES标称温度系数：45 ppm/ °C
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
标称总电阻：100000 Ω宽度：1.6 mm
Base Number Matches：1

AD5160BRJ100-R2 数据手册

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AD5160  
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS  
(VDD = +5V 10%, or +3V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)  
Table 3.  
Parameter  
Symbol  
Conditions  
Min Typ1 Max Unit  
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)  
Clock Frequency  
Input Clock Pulsewidth  
Data Setup Time  
Data Hold Time  
fCLK  
tCH, tCL  
tDS  
25  
MHz  
ns  
ns  
Clock level high or low  
20  
5
5
tDH  
ns  
CS  
tCSS  
15  
40  
0
ns  
Setup Time  
CS  
tCSW  
tCSH0  
tCSH1  
tCS1  
ns  
High Pulsewidth  
CS  
CS  
ns  
CLK Fall to  
CLK Fall to  
CS  
Fall Hold Time  
Rise Hold Time  
0
ns  
10  
ns  
Rise to Clock Rise Setup  
NOTES  
1 Typical specifications represent average readings at +25°C and VDD = 5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.  
3 VAB = VDD, Wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test.  
ꢀ Measured at the A terminal. The A terminal is open circuited in shutdown mode.  
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
9 All dynamic characteristics use VDD = 5 V.  
10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage  
level of 1.5 V.  
ABSOLUTE MAXIMUM RATINGS1  
(TA = +25°C, unless otherwise noted.)  
Table 4.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device at these or  
any other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter  
VDD to GND  
VA, VB, VW to GND  
Value  
–0.3 V to +ꢀ V  
VDD  
1
IMAX  
20 mA  
Digital Inputs and Output Voltage to GND 0 V to +ꢀ V  
Operating Temperature Range  
Maximum Junction Temperature (TJMAX  
Storage Temperature  
–40°C to +125°C  
)
150°C  
–65°C to +150°C  
300°C  
Lead Temperature (Soldering, 10 sec)  
Thermal Resistance2 θJA: MSOP-10  
230°C/W  
NOTES  
1 Maximum terminal current is bounded by the maximum current handling of  
the switches, maximum power dissipation of the package, and maximum  
applied voltage across any two of the A, B, and W terminals at a given  
resistance.  
2 Package power dissipation = (TJMAX – TA)/θJA  
.
Rev. 0 | Page 5 of 16  
 
 
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