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AD5110BCPZ80-RL7 PDF预览

AD5110BCPZ80-RL7

更新时间: 2024-01-11 06:29:42
品牌 Logo 应用领域
亚德诺 - ADI 数字电位计
页数 文件大小 规格书
28页 517K
描述
Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer

AD5110BCPZ80-RL7 数据手册

 浏览型号AD5110BCPZ80-RL7的Datasheet PDF文件第5页浏览型号AD5110BCPZ80-RL7的Datasheet PDF文件第6页浏览型号AD5110BCPZ80-RL7的Datasheet PDF文件第7页浏览型号AD5110BCPZ80-RL7的Datasheet PDF文件第9页浏览型号AD5110BCPZ80-RL7的Datasheet PDF文件第10页浏览型号AD5110BCPZ80-RL7的Datasheet PDF文件第11页 
AD5110/AD5112/AD5114  
Data Sheet  
Parameter  
Symbol  
Test Conditions/Comments  
Min  
Typ1 Max  
Unit  
POWER SUPPLIES  
Single-Supply Power Range  
Logic Supply Range  
Positive Supply Current  
EEMEM Store Current3, 6  
EEMEM Read Current3,7  
Logic Supply Current  
Power Dissipation8  
2.3  
1.8  
5.5  
VDD  
V
V
IDD  
VDD = 5 V  
750  
2
nA  
mA  
μA  
nA  
μW  
IDD_NVM_STORE  
IDD_NVM_READ  
ILOGIC  
PDISS  
PSR  
320  
30  
5
VIH = VLOGIC or VIL = GND  
VIH = VLOGIC or VIL = GND  
∆VDD/∆VSS = 5 V 10%  
RAB = 10 kΩ  
Power Supply Rejection3  
−50  
−64  
dB  
dB  
RAB = 80 kΩ  
DYNAMIC CHARACTERISTICS3, 9  
Bandwidth  
BW  
Code = half scale, −3 dB  
RAB = 10 kΩ  
2
200  
MHz  
kHz  
RAB = 80 kΩ  
Total Harmonic Distortion  
THD  
VA = VDD/2 + 1 V rms,  
VB = VDD/2, f = 1 kHz,  
code = half scale  
RAB = 10 kΩ  
RAB = 80 kΩ  
−80  
−85  
dB  
dB  
VW Settling Time  
ts  
VA = 5 V, VB = 0 V, 0.5 LSB  
error band  
RAB = 10 kΩ  
RAB = 80 kΩ  
μs  
μs  
2.7  
9.5  
Resistor Noise Density  
eN_WB  
Code = half scale, TA = 25°C,  
f = 100 kHz  
RAB = 10 kΩ  
RAB = 80 kΩ  
9
20  
nV/√Hz  
nV/√Hz  
FLASH/EE MEMORY RELIABILITY3  
Endurance10  
TA = 25°C  
1
MCycles  
kCycles  
Years  
100  
Data Retention11  
50  
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.  
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.  
3 Guaranteed by design and characterization, not subject to production test.  
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits  
of 1 LSB maximum are guaranteed monotonic operating conditions.  
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.  
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.  
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).  
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.  
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.  
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV  
derates with junction temperature in the Flash/EE memory.  
Rev. 0 | Page 8 of 28  
 

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